| OLD | NEW |
| 1 /* This file is automatically generated */ | 1 /* This file is automatically generated */ |
| 2 | 2 |
| 3 struct { | 3 struct s_tpm_extend_cmd{ |
| 4 uint8_t buffer[34]; | 4 uint8_t buffer[34]; |
| 5 uint8_t* pcrNum; | 5 uint16_t pcrNum; |
| 6 uint8_t* inDigest; | 6 uint16_t inDigest; |
| 7 } tpm_extend_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, }, | 7 } tpm_extend_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, }, |
| 8 tpm_extend_cmd.buffer + 10, tpm_extend_cmd.buffer + 14, }; | 8 10, 14, }; |
| 9 | 9 |
| 10 struct { | 10 struct s_tpm_getpermissions_cmd{ |
| 11 uint8_t buffer[22]; | 11 uint8_t buffer[22]; |
| 12 uint8_t* index; | 12 uint16_t index; |
| 13 } tpm_getpermissions_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65
, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x4, }, | 13 } tpm_getpermissions_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65
, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x4, }, |
| 14 tpm_getpermissions_cmd.buffer + 18, }; | 14 18, }; |
| 15 | 15 |
| 16 struct { | 16 struct s_tpm_getflags_cmd{ |
| 17 uint8_t buffer[22]; | 17 uint8_t buffer[22]; |
| 18 } tpm_getflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0,
0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x8, }, | 18 } tpm_getflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0,
0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x8, }, |
| 19 }; | 19 }; |
| 20 | 20 |
| 21 struct { | 21 struct s_tpm_physicalsetdeactivated_cmd{ |
| 22 uint8_t buffer[11]; | 22 uint8_t buffer[11]; |
| 23 uint8_t* deactivated; | 23 uint16_t deactivated; |
| 24 } tpm_physicalsetdeactivated_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x
0, 0x72, }, | 24 } tpm_physicalsetdeactivated_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x
0, 0x72, }, |
| 25 tpm_physicalsetdeactivated_cmd.buffer + 10, }; | 25 10, }; |
| 26 | 26 |
| 27 struct { | 27 struct s_tpm_physicalenable_cmd{ |
| 28 uint8_t buffer[10]; | 28 uint8_t buffer[10]; |
| 29 } tpm_physicalenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f,
}, | 29 } tpm_physicalenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f,
}, |
| 30 }; | 30 }; |
| 31 | 31 |
| 32 struct { | 32 struct s_tpm_physicaldisable_cmd{ |
| 33 uint8_t buffer[10]; | 33 uint8_t buffer[10]; |
| 34 } tpm_physicaldisable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70
, }, | 34 } tpm_physicaldisable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70
, }, |
| 35 }; | 35 }; |
| 36 | 36 |
| 37 struct { | 37 struct s_tpm_forceclear_cmd{ |
| 38 uint8_t buffer[10]; | 38 uint8_t buffer[10]; |
| 39 } tpm_forceclear_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, }, | 39 } tpm_forceclear_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, }, |
| 40 }; | 40 }; |
| 41 | 41 |
| 42 struct { | 42 struct s_tpm_readpubek_cmd{ |
| 43 uint8_t buffer[30]; | 43 uint8_t buffer[30]; |
| 44 } tpm_readpubek_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, }, | 44 } tpm_readpubek_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, }, |
| 45 }; | 45 }; |
| 46 | 46 |
| 47 struct { | 47 struct s_tpm_continueselftest_cmd{ |
| 48 uint8_t buffer[10]; | 48 uint8_t buffer[10]; |
| 49 } tpm_continueselftest_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5
3, }, | 49 } tpm_continueselftest_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5
3, }, |
| 50 }; | 50 }; |
| 51 | 51 |
| 52 struct { | 52 struct s_tpm_selftestfull_cmd{ |
| 53 uint8_t buffer[10]; | 53 uint8_t buffer[10]; |
| 54 } tpm_selftestfull_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, }
, | 54 } tpm_selftestfull_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, }
, |
| 55 }; | 55 }; |
| 56 | 56 |
| 57 struct { | 57 struct s_tpm_startup_cmd{ |
| 58 uint8_t buffer[12]; | 58 uint8_t buffer[12]; |
| 59 } tpm_startup_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0
x1, }, | 59 } tpm_startup_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0
x1, }, |
| 60 }; | 60 }; |
| 61 | 61 |
| 62 struct { | 62 struct s_tpm_pplock_cmd{ |
| 63 uint8_t buffer[12]; | 63 uint8_t buffer[12]; |
| 64 } tpm_pplock_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x
4, }, | 64 } tpm_pplock_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x
4, }, |
| 65 }; | 65 }; |
| 66 | 66 |
| 67 struct { | 67 struct s_tpm_ppassert_cmd{ |
| 68 uint8_t buffer[12]; | 68 uint8_t buffer[12]; |
| 69 } tpm_ppassert_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0,
0x8, }, | 69 } tpm_ppassert_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0,
0x8, }, |
| 70 }; | 70 }; |
| 71 | 71 |
| 72 struct { | 72 struct s_tpm_nv_read_cmd{ |
| 73 uint8_t buffer[22]; | 73 uint8_t buffer[22]; |
| 74 uint8_t* index; | 74 uint16_t index; |
| 75 uint8_t* length; | 75 uint16_t length; |
| 76 } tpm_nv_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, }, | 76 } tpm_nv_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, }, |
| 77 tpm_nv_read_cmd.buffer + 10, tpm_nv_read_cmd.buffer + 18, }; | 77 10, 18, }; |
| 78 | 78 |
| 79 struct { | 79 struct s_tpm_nv_write_cmd{ |
| 80 uint8_t buffer[256]; | 80 uint8_t buffer[256]; |
| 81 uint8_t* index; | 81 uint16_t index; |
| 82 uint8_t* length; | 82 uint16_t length; |
| 83 uint8_t* data; | 83 uint16_t data; |
| 84 } tpm_nv_write_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, }, | 84 } tpm_nv_write_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, }, |
| 85 tpm_nv_write_cmd.buffer + 10, tpm_nv_write_cmd.buffer + 18, tpm_nv_write_cmd.buf
fer + 22, }; | 85 10, 18, 22, }; |
| 86 | 86 |
| 87 struct { | 87 struct s_tpm_nv_definespace_cmd{ |
| 88 uint8_t buffer[101]; | 88 uint8_t buffer[101]; |
| 89 uint8_t* index; | 89 uint16_t index; |
| 90 uint8_t* perm; | 90 uint16_t perm; |
| 91 uint8_t* size; | 91 uint16_t size; |
| 92 } tpm_nv_definespace_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0xcc
, 0x0, 0x18, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x17, }, | 92 } tpm_nv_definespace_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0xcc
, 0x0, 0x18, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x17, }, |
| 93 tpm_nv_definespace_cmd.buffer + 12, tpm_nv_definespace_cmd.buffer + 70, tpm_nv_d
efinespace_cmd.buffer + 77, }; | 93 12, 70, 77, }; |
| 94 | 94 |
| 95 const int kWriteInfoLength = 12; | 95 const int kWriteInfoLength = 12; |
| 96 const int kNvDataPublicPermissionsOffset = 60; | 96 const int kNvDataPublicPermissionsOffset = 60; |
| OLD | NEW |