[binutils] Bump binutils to 2.20.1

binutils/gas/config/tc-ppc.c

Index: binutils/gas/config/tc-ppc.c
diff --git a/binutils/gas/config/tc-ppc.c b/binutils/gas/config/tc-ppc.c
index 493bfe5546bd2a2b02663957955acd7ddfee0214..77134393809442cb43aad06ca9e37ec042ed21d2 100644
--- a/binutils/gas/config/tc-ppc.c
+++ b/binutils/gas/config/tc-ppc.c
@@ -108,6 +108,7 @@ static void ppc_change_csect (symbolS *, offsetT);
 static void ppc_function (int);
 static void ppc_extern (int);
 static void ppc_lglobl (int);
+static void ppc_ref (int);
 static void ppc_section (int);
 static void ppc_named_section (int);
 static void ppc_stabx (int);
@@ -212,6 +213,7 @@ const pseudo_typeS md_pseudo_table[] =
   { "extern",	ppc_extern,	0 },
   { "function",	ppc_function,	0 },
   { "lglobl",	ppc_lglobl,	0 },
+  { "ref",	ppc_ref,	0 },
   { "rename",	ppc_rename,	0 },
   { "section",	ppc_named_section, 0 },
   { "stabx",	ppc_stabx,	0 },
@@ -1197,10 +1199,11 @@ PowerPC options:\n\
 -mppc64bridge		generate code for PowerPC 64, including bridge insns\n\
 -mbooke			generate code for 32-bit PowerPC BookE\n\
 -ma2			generate code for A2 architecture\n\
--mpower4		generate code for Power4 architecture\n\
--mpower5		generate code for Power5 architecture\n\
--mpower6		generate code for Power6 architecture\n\
--mpower7		generate code for Power7 architecture\n\
+-mpower4, -mpwr4	generate code for Power4 architecture\n\
+-mpower5, -mpwr5, -mpwr5x\n\
+			generate code for Power5 architecture\n\
+-mpower6, -mpwr6	generate code for Power6 architecture\n\
+-mpower7, -mpwr7	generate code for Power7 architecture\n\
 -mcell			generate code for Cell Broadband Engine architecture\n\
 -mcom			generate code Power/PowerPC common instructions\n\
 -many			generate code for any architecture (PWR/PWRX/PPC)\n"));
@@ -3552,6 +3555,58 @@ ppc_lglobl (int ignore ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
+/* The .ref pseudo-op.  It takes a list of symbol names and inserts R_REF
+   relocations at the beginning of the current csect.
+
+   (In principle, there's no reason why the relocations _have_ to be at
+   the beginning.  Anywhere in the csect would do.  However, inserting
+   at the beginning is what the native assmebler does, and it helps to
+   deal with cases where the .ref statements follow the section contents.)
+
+   ??? .refs don't work for empty .csects.  However, the native assembler
+   doesn't report an error in this case, and neither yet do we.  */
+
+static void
+ppc_ref (int ignore ATTRIBUTE_UNUSED)
+{
+  char *name;
+  char c;
+
+  if (ppc_current_csect == NULL)
+    {
+      as_bad (_(".ref outside .csect"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  do
+    {
+      name = input_line_pointer;
+      c = get_symbol_end ();
+
+      fix_at_start (symbol_get_frag (ppc_current_csect), 0,
+		    symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE);
+
+      *input_line_pointer = c;
+      SKIP_WHITESPACE ();
+      c = *input_line_pointer;
+      if (c == ',')
+	{
+	  input_line_pointer++;
+	  SKIP_WHITESPACE ();
+	  if (is_end_of_line[(unsigned char) *input_line_pointer])
+	    {
+	      as_bad (_("missing symbol name"));
+	      ignore_rest_of_line ();
+	      return;
+	    }
+	}
+    }
+  while (c == ',');
+
+  demand_empty_rest_of_line ();
+}
+
 /* The .rename pseudo-op.  The RS/6000 assembler can rename symbols,
    although I don't know why it bothers.  */
 
@@ -6025,6 +6080,11 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 			      PPC_HA (value), 2);
 	  break;
 
+#ifdef OBJ_XCOFF
+	case BFD_RELOC_NONE:
+	  break;
+#endif
+
 #ifdef OBJ_ELF
 	case BFD_RELOC_PPC64_HIGHER:
 	  if (fixP->fx_pcrel)