Fixed a couple of issues with store inlining on arm....

src/arm/ic-arm.cc

 // Copyright 2006-2008 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 998 matching lines @@
         ldr_map_instr_address + 3 * Assembler::kInstrSize;
     Instr str_property_instr = Assembler::instr_at(str_property_instr_address);
     ASSERT(Assembler::IsStrRegisterImmediate(str_property_instr));
     str_property_instr = Assembler::SetStrRegisterImmediateOffset(
         str_property_instr, offset - kHeapObjectTag);
     Assembler::instr_at_put(str_property_instr_address, str_property_instr);
 
     // Patch the offset in the add instruction that is part of the
     // write barrier.
     Address add_offset_instr_address =
-        str_property_instr_address + 4 * Assembler::kInstrSize;
+        str_property_instr_address + Assembler::kInstrSize;
     Instr add_offset_instr = Assembler::instr_at(add_offset_instr_address);
     ASSERT(Assembler::IsAddRegisterImmediate(add_offset_instr));
     add_offset_instr = Assembler::SetAddRegisterImmediateOffset(
         add_offset_instr, offset - kHeapObjectTag);
     Assembler::instr_at_put(add_offset_instr_address, add_offset_instr);
 
     // Indicate that code has changed.
-    CPU::FlushICache(str_property_instr_address, 5 * Assembler::kInstrSize);
+    CPU::FlushICache(str_property_instr_address, 2 * Assembler::kInstrSize);
   }
 
   // Patch the map check.
   Assembler::set_target_address_at(ldr_map_instr_address,
                                    reinterpret_cast<Address>(map));
 
   return true;
 }
 
 
@@ skipping 1211 matching lines @@
   GenerateMiss(masm);
 }
 
 
 #undef __
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM