Fixed a couple of issues with store inlining on arm....

src/arm/codegen-arm.cc

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 133 matching lines @@
 }
 
 
 TypeInfoCodeGenState::~TypeInfoCodeGenState() {
   owner()->set_type_info(slot_, old_type_info_);
 }
 
 // -------------------------------------------------------------------------
 // CodeGenerator implementation
 
+int CodeGenerator::inlined_write_barrier_size_ = -1;
+
 CodeGenerator::CodeGenerator(MacroAssembler* masm)
     : deferred_(8),
       masm_(masm),
       info_(NULL),
       frame_(NULL),
       allocator_(NULL),
       cc_reg_(al),
       state_(NULL),
       loop_nesting_(0),
       type_info_(NULL),
@@ skipping 6054 matching lines @@
 
   virtual void Generate();
 
  private:
   Register value_;
   Register receiver_;
   Handle<String> name_;
 };
 
 
+// Takes value in r0, receiver in r1 and returns the result (the
+// value) in r0.
 void DeferredReferenceSetNamedValue::Generate() {
+  // Record the entry frame and spill.
+  VirtualFrame copied_frame(*frame_state()->frame());
+  copied_frame.SpillAll();
+
   // Ensure value in r0, receiver in r1 to match store ic calling
   // convention.
   ASSERT(value_.is(r0) && receiver_.is(r1));
   __ mov(r2, Operand(name_));
 
   // The rest of the instructions in the deferred code must be together.
   { Assembler::BlockConstPoolScope block_const_pool(masm_);
     // Call keyed store IC. It has the arguments value, key and receiver in r0,
     // r1 and r2.
     Handle<Code> ic(Builtins::builtin(Builtins::StoreIC_Initialize));
     __ Call(ic, RelocInfo::CODE_TARGET);
     // The call must be followed by a nop instruction to indicate that the
     // named store has been inlined.
     __ nop(PROPERTY_ACCESS_INLINED);
 
+    // Go back to the frame we entered with. The instructions
+    // generated by this merge are skipped over by the inline store
+    // patching mechanism when looking for the branch instruction that
+    // tells it where the code to patch is.
+    copied_frame.MergeTo(frame_state()->frame());
+
     // Block the constant pool for one more instruction after leaving this
     // constant pool block scope to include the branch instruction ending the
     // deferred code.
     __ BlockConstPoolFor(1);
   }
 }
 
 
 // Consumes the top of stack (the receiver) and pushes the result instead.
 void CodeGenerator::EmitNamedLoad(Handle<String> name, bool is_contextual) {
@@ skipping 104 matching lines @@
       Label check_inlined_codesize;
       masm_->bind(&check_inlined_codesize);
 #endif
       __ mov(scratch0, Operand(Factory::null_value()));
       __ cmp(scratch0, scratch1);
       deferred->Branch(ne);
 
       int offset = 0;
       __ str(value, MemOperand(receiver, offset));
 
-      // Update the write barrier.
-      __ RecordWrite(receiver, Operand(offset), scratch0, scratch1);
+      // Update the write barrier and record its size. We do not use
+      // the RecordWrite macro here because we want the offset
+      // addition instruction first to make it easy to patch.
+      Label record_write_start, record_write_done;
+      __ bind(&record_write_start);
+      // Add offset into the object.
+      __ add(scratch0, receiver, Operand(offset));
+      // Test that the object is not in the new space.  We cannot set
+      // region marks for new space pages.
+      __ InNewSpace(receiver, scratch1, eq, &record_write_done);
+      // Record the actual write.
+      __ RecordWriteHelper(receiver, scratch0, scratch1);
+      __ bind(&record_write_done);
+      // Clobber all input registers when running with the debug-code flag
+      // turned on to provoke errors.
+      if (FLAG_debug_code) {
+        __ mov(receiver, Operand(BitCast<int32_t>(kZapValue)));
+        __ mov(scratch0, Operand(BitCast<int32_t>(kZapValue)));
+        __ mov(scratch1, Operand(BitCast<int32_t>(kZapValue)));
+      }
+      // Check that this is the first inlined write barrier or that
+      // this inlined write barrier has the same size as all the other
+      // inlined write barriers.
+      ASSERT((inlined_write_barrier_size_ == -1) ||
+             (inlined_write_barrier_size_ ==
+              masm()->InstructionsGeneratedSince(&record_write_start)));
+      inlined_write_barrier_size_ =
+          masm()->InstructionsGeneratedSince(&record_write_start);
+
       // Make sure that the expected number of instructions are generated.
       ASSERT_EQ(GetInlinedNamedStoreInstructionsAfterPatch(),
-                masm_->InstructionsGeneratedSince(&check_inlined_codesize));
+                masm()->InstructionsGeneratedSince(&check_inlined_codesize));
     }
     deferred->BindExit();
   }
   ASSERT_EQ(expected_height, frame()->height());
 }
 
 
 void CodeGenerator::EmitKeyedLoad() {
   if (loop_nesting() == 0) {
     Comment cmnt(masm_, "[ Load from keyed property");
@@ skipping 4965 matching lines @@
   __ bind(&string_add_runtime);
   __ TailCallRuntime(Runtime::kStringAdd, 2, 1);
 }
 
 
 #undef __
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM