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Issue 2885002: ARM: Use the vsqrt instruction when available... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 5 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
11 // with the distribution. 11 // with the distribution.
12 // * Neither the name of Google Inc. nor the names of its 12 // * Neither the name of Google Inc. nor the names of its
13 // contributors may be used to endorse or promote products derived 13 // contributors may be used to endorse or promote products derived
14 // from this software without specific prior written permission. 14 // from this software without specific prior written permission.
15 // 15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 27
28 #include <stdlib.h> 28 #include <stdlib.h>
29 #include <math.h>
29 #include <cstdarg> 30 #include <cstdarg>
30 #include "v8.h" 31 #include "v8.h"
31 32
32 #if defined(V8_TARGET_ARCH_ARM) 33 #if defined(V8_TARGET_ARCH_ARM)
33 34
34 #include "disasm.h" 35 #include "disasm.h"
35 #include "assembler.h" 36 #include "assembler.h"
36 #include "arm/constants-arm.h" 37 #include "arm/constants-arm.h"
37 #include "arm/simulator-arm.h" 38 #include "arm/simulator-arm.h"
38 39
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2255 // The Following ARMv7 VFPv instructions are currently supported. 2256 // The Following ARMv7 VFPv instructions are currently supported.
2256 // vmov :Sn = Rt 2257 // vmov :Sn = Rt
2257 // vmov :Rt = Sn 2258 // vmov :Rt = Sn
2258 // vcvt: Dd = Sm 2259 // vcvt: Dd = Sm
2259 // vcvt: Sd = Dm 2260 // vcvt: Sd = Dm
2260 // Dd = vadd(Dn, Dm) 2261 // Dd = vadd(Dn, Dm)
2261 // Dd = vsub(Dn, Dm) 2262 // Dd = vsub(Dn, Dm)
2262 // Dd = vmul(Dn, Dm) 2263 // Dd = vmul(Dn, Dm)
2263 // Dd = vdiv(Dn, Dm) 2264 // Dd = vdiv(Dn, Dm)
2264 // vcmp(Dd, Dm) 2265 // vcmp(Dd, Dm)
2265 // VMRS 2266 // vmrs
2267 // Dd = vsqrt(Dm)
2266 void Simulator::DecodeTypeVFP(Instr* instr) { 2268 void Simulator::DecodeTypeVFP(Instr* instr) {
2267 ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) ); 2269 ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) );
2268 ASSERT(instr->Bits(11, 9) == 0x5); 2270 ASSERT(instr->Bits(11, 9) == 0x5);
2269 2271
2270 int vm = instr->VmField(); 2272 int vm = instr->VmField();
2271 int vd = instr->VdField(); 2273 int vd = instr->VdField();
2272 int vn = instr->VnField(); 2274 int vn = instr->VnField();
2273 2275
2274 if (instr->Bit(4) == 0) { 2276 if (instr->Bit(4) == 0) {
2275 if (instr->Opc1Field() == 0x7) { 2277 if (instr->Opc1Field() == 0x7) {
2276 // Other data processing instructions 2278 // Other data processing instructions
2277 if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) { 2279 if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
2278 DecodeVCVTBetweenDoubleAndSingle(instr); 2280 DecodeVCVTBetweenDoubleAndSingle(instr);
2279 } else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) { 2281 } else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) {
2280 DecodeVCVTBetweenFloatingPointAndInteger(instr); 2282 DecodeVCVTBetweenFloatingPointAndInteger(instr);
2281 } else if (((instr->Opc2Field() >> 1) == 0x6) && 2283 } else if (((instr->Opc2Field() >> 1) == 0x6) &&
2282 (instr->Opc3Field() & 0x1)) { 2284 (instr->Opc3Field() & 0x1)) {
2283 DecodeVCVTBetweenFloatingPointAndInteger(instr); 2285 DecodeVCVTBetweenFloatingPointAndInteger(instr);
2284 } else if (((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) && 2286 } else if (((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
2285 (instr->Opc3Field() & 0x1)) { 2287 (instr->Opc3Field() & 0x1)) {
2286 DecodeVCMP(instr); 2288 DecodeVCMP(instr);
2289 } else if (((instr->Opc2Field() == 0x1)) && (instr->Opc3Field() == 0x3)) {
2290 // vsqrt
2291 double dm_value = get_double_from_d_register(vm);
2292 double dd_value = sqrt(dm_value);
2293 set_d_register_from_double(vd, dd_value);
2287 } else { 2294 } else {
2288 UNREACHABLE(); // Not used by V8. 2295 UNREACHABLE(); // Not used by V8.
2289 } 2296 }
2290 } else if (instr->Opc1Field() == 0x3) { 2297 } else if (instr->Opc1Field() == 0x3) {
2291 if (instr->SzField() != 0x1) { 2298 if (instr->SzField() != 0x1) {
2292 UNREACHABLE(); // Not used by V8. 2299 UNREACHABLE(); // Not used by V8.
2293 } 2300 }
2294 2301
2295 if (instr->Opc3Field() & 0x1) { 2302 if (instr->Opc3Field() & 0x1) {
2296 // vsub 2303 // vsub
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2762 uintptr_t address = *stack_slot; 2769 uintptr_t address = *stack_slot;
2763 set_register(sp, current_sp + sizeof(uintptr_t)); 2770 set_register(sp, current_sp + sizeof(uintptr_t));
2764 return address; 2771 return address;
2765 } 2772 }
2766 2773
2767 } } // namespace assembler::arm 2774 } } // namespace assembler::arm
2768 2775
2769 #endif // __arm__ 2776 #endif // __arm__
2770 2777
2771 #endif // V8_TARGET_ARCH_ARM 2778 #endif // V8_TARGET_ARCH_ARM
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