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Issue 2885002: ARM: Use the vsqrt instruction when available... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 5 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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981 void vdiv(const DwVfpRegister dst, 981 void vdiv(const DwVfpRegister dst,
982 const DwVfpRegister src1, 982 const DwVfpRegister src1,
983 const DwVfpRegister src2, 983 const DwVfpRegister src2,
984 const Condition cond = al); 984 const Condition cond = al);
985 void vcmp(const DwVfpRegister src1, 985 void vcmp(const DwVfpRegister src1,
986 const DwVfpRegister src2, 986 const DwVfpRegister src2,
987 const SBit s = LeaveCC, 987 const SBit s = LeaveCC,
988 const Condition cond = al); 988 const Condition cond = al);
989 void vmrs(const Register dst, 989 void vmrs(const Register dst,
990 const Condition cond = al); 990 const Condition cond = al);
991 void vsqrt(const DwVfpRegister dst,
992 const DwVfpRegister src,
993 const Condition cond = al);
991 994
992 // Pseudo instructions 995 // Pseudo instructions
993 void nop(int type = 0); 996 void nop(int type = 0);
994 997
995 void push(Register src, Condition cond = al) { 998 void push(Register src, Condition cond = al) {
996 str(src, MemOperand(sp, 4, NegPreIndex), cond); 999 str(src, MemOperand(sp, 4, NegPreIndex), cond);
997 } 1000 }
998 1001
999 void pop(Register dst, Condition cond = al) { 1002 void pop(Register dst, Condition cond = al) {
1000 ldr(dst, MemOperand(sp, 4, PostIndex), cond); 1003 ldr(dst, MemOperand(sp, 4, PostIndex), cond);
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1214 1217
1215 friend class RegExpMacroAssemblerARM; 1218 friend class RegExpMacroAssemblerARM;
1216 friend class RelocInfo; 1219 friend class RelocInfo;
1217 friend class CodePatcher; 1220 friend class CodePatcher;
1218 friend class BlockConstPoolScope; 1221 friend class BlockConstPoolScope;
1219 }; 1222 };
1220 1223
1221 } } // namespace v8::internal 1224 } } // namespace v8::internal
1222 1225
1223 #endif // V8_ARM_ASSEMBLER_ARM_H_ 1226 #endif // V8_ARM_ASSEMBLER_ARM_H_
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