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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2105 void Assembler::vmrs(Register dst, Condition cond) { | 2105 void Assembler::vmrs(Register dst, Condition cond) { |
2106 // Instruction details available in ARM DDI 0406A, A8-652. | 2106 // Instruction details available in ARM DDI 0406A, A8-652. |
2107 // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) | | 2107 // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) | |
2108 // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) | 2108 // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) |
2109 ASSERT(CpuFeatures::IsEnabled(VFP3)); | 2109 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
2110 emit(cond | 0xE*B24 | 0xF*B20 | B16 | | 2110 emit(cond | 0xE*B24 | 0xF*B20 | B16 | |
2111 dst.code()*B12 | 0xA*B8 | B4); | 2111 dst.code()*B12 | 0xA*B8 | B4); |
2112 } | 2112 } |
2113 | 2113 |
2114 | 2114 |
| 2115 |
| 2116 void Assembler::vsqrt(const DwVfpRegister dst, |
| 2117 const DwVfpRegister src, |
| 2118 const Condition cond) { |
| 2119 // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0001 (19-16) | |
| 2120 // Vd(15-12) | 101(11-9) | sz(8)=1 | 11 (7-6) | M(5)=? | 0(4) | Vm(3-0) |
| 2121 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2122 emit(cond | 0xE*B24 | B23 | 0x3*B20 | B16 | |
| 2123 dst.code()*B12 | 0x5*B9 | B8 | 3*B6 | src.code()); |
| 2124 } |
| 2125 |
| 2126 |
2115 // Pseudo instructions. | 2127 // Pseudo instructions. |
2116 void Assembler::nop(int type) { | 2128 void Assembler::nop(int type) { |
2117 // This is mov rx, rx. | 2129 // This is mov rx, rx. |
2118 ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop. | 2130 ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop. |
2119 emit(al | 13*B21 | type*B12 | type); | 2131 emit(al | 13*B21 | type*B12 | type); |
2120 } | 2132 } |
2121 | 2133 |
2122 | 2134 |
2123 bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) { | 2135 bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) { |
2124 uint32_t dummy1; | 2136 uint32_t dummy1; |
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2385 | 2397 |
2386 // Since a constant pool was just emitted, move the check offset forward by | 2398 // Since a constant pool was just emitted, move the check offset forward by |
2387 // the standard interval. | 2399 // the standard interval. |
2388 next_buffer_check_ = pc_offset() + kCheckConstInterval; | 2400 next_buffer_check_ = pc_offset() + kCheckConstInterval; |
2389 } | 2401 } |
2390 | 2402 |
2391 | 2403 |
2392 } } // namespace v8::internal | 2404 } } // namespace v8::internal |
2393 | 2405 |
2394 #endif // V8_TARGET_ARCH_ARM | 2406 #endif // V8_TARGET_ARCH_ARM |
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