| Index: src/arm/assembler-arm.cc
|
| ===================================================================
|
| --- src/arm/assembler-arm.cc (revision 4988)
|
| +++ src/arm/assembler-arm.cc (working copy)
|
| @@ -1763,8 +1763,16 @@
|
| // Vdst(15-12) | 1011(11-8) | offset
|
| ASSERT(CpuFeatures::IsEnabled(VFP3));
|
| ASSERT(offset % 4 == 0);
|
| - ASSERT((offset / 4) < 256);
|
| - emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 |
|
| + ASSERT(((offset / 4) < 256) && ((-offset / 4) < 256));
|
| +
|
| + // Handle negative offsets.
|
| + int sign = 0xD9;
|
| + if (offset < 0) {
|
| + offset = -offset;
|
| + sign = 0xD1;
|
| + }
|
| +
|
| + emit(cond | sign*B20 | base.code()*B16 | dst.code()*B12 |
|
| 0xB*B8 | ((offset / 4) & 255));
|
| }
|
|
|
| @@ -1779,8 +1787,16 @@
|
| // Vdst(15-12) | 1010(11-8) | offset
|
| ASSERT(CpuFeatures::IsEnabled(VFP3));
|
| ASSERT(offset % 4 == 0);
|
| - ASSERT((offset / 4) < 256);
|
| - emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 |
|
| + ASSERT(((offset / 4) < 256) && ((-offset / 4) < 256));
|
| +
|
| + // Handle negative offsets.
|
| + int sign = 0xD9;
|
| + if (offset < 0) {
|
| + offset = -offset;
|
| + sign = 0xD1;
|
| + }
|
| +
|
| + emit(cond | sign*B20 | base.code()*B16 | dst.code()*B12 |
|
| 0xA*B8 | ((offset / 4) & 255));
|
| }
|
|
|
| @@ -1795,8 +1811,16 @@
|
| // Vsrc(15-12) | 1011(11-8) | (offset/4)
|
| ASSERT(CpuFeatures::IsEnabled(VFP3));
|
| ASSERT(offset % 4 == 0);
|
| - ASSERT((offset / 4) < 256);
|
| - emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 |
|
| + ASSERT(((offset / 4) < 256) && ((-offset / 4) < 256));
|
| +
|
| + // Handle negative offsets.
|
| + int sign = 0xD8;
|
| + if (offset < 0) {
|
| + offset = -offset;
|
| + sign = 0xD0;
|
| + }
|
| +
|
| + emit(cond | sign*B20 | base.code()*B16 | src.code()*B12 |
|
| 0xB*B8 | ((offset / 4) & 255));
|
| }
|
|
|
|
|