Make use of VFP to convert/write 32bits int to heapnumbers. Extended...

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1745 matching lines @@
 void Assembler::vldr(const DwVfpRegister dst,
                      const Register base,
                      int offset,
                      const Condition cond) {
   // Ddst = MEM(Rbase + offset).
   // Instruction details available in ARM DDI 0406A, A8-628.
   // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) |
   // Vdst(15-12) | 1011(11-8) | offset
   ASSERT(CpuFeatures::IsEnabled(VFP3));
   ASSERT(offset % 4 == 0);
-  ASSERT((offset / 4) < 256);
-  emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 |
+  ASSERT(((offset / 4) < 256) && ((-offset / 4) < 256));
+
+  // Handle negative offsets.
+  int sign = 0xD9;
+  if (offset < 0) {
+    offset = -offset;
+    sign = 0xD1;
+  }
+
+  emit(cond | sign*B20 | base.code()*B16 | dst.code()*B12 |
        0xB*B8 | ((offset / 4) & 255));
 }
 
 
 void Assembler::vldr(const SwVfpRegister dst,
                      const Register base,
                      int offset,
                      const Condition cond) {
   // Sdst = MEM(Rbase + offset).
   // Instruction details available in ARM DDI 0406A, A8-628.
   // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) |
   // Vdst(15-12) | 1010(11-8) | offset
   ASSERT(CpuFeatures::IsEnabled(VFP3));
   ASSERT(offset % 4 == 0);
-  ASSERT((offset / 4) < 256);
-  emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 |
+  ASSERT(((offset / 4) < 256) && ((-offset / 4) < 256));
+
+  // Handle negative offsets.
+  int sign = 0xD9;
+  if (offset < 0) {
+    offset = -offset;
+    sign = 0xD1;
+  }
+
+  emit(cond | sign*B20 | base.code()*B16 | dst.code()*B12 |
        0xA*B8 | ((offset / 4) & 255));
 }
 
 
 void Assembler::vstr(const DwVfpRegister src,
                      const Register base,
                      int offset,
                      const Condition cond) {
   // MEM(Rbase + offset) = Dsrc.
   // Instruction details available in ARM DDI 0406A, A8-786.
   // cond(31-28) | 1101(27-24)| 1000(23-20) | | Rbase(19-16) |
   // Vsrc(15-12) | 1011(11-8) | (offset/4)
   ASSERT(CpuFeatures::IsEnabled(VFP3));
   ASSERT(offset % 4 == 0);
-  ASSERT((offset / 4) < 256);
-  emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 |
+  ASSERT(((offset / 4) < 256) && ((-offset / 4) < 256));
+
+  // Handle negative offsets.
+  int sign = 0xD8;
+  if (offset < 0) {
+    offset = -offset;
+    sign = 0xD0;
+  }
+
+  emit(cond | sign*B20 | base.code()*B16 | src.code()*B12 |
        0xB*B8 | ((offset / 4) & 255));
 }
 
 
 void Assembler::vmov(const DwVfpRegister dst,
                      const Register src1,
                      const Register src2,
                      const Condition cond) {
   // Dm = <Rt,Rt2>.
   // Instruction details available in ARM DDI 0406A, A8-646.
@@ skipping 587 matching lines @@
 
   // Since a constant pool was just emitted, move the check offset forward by
   // the standard interval.
   next_buffer_check_ = pc_offset() + kCheckConstInterval;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM