Add movw and movt support for ARMv7. This includes some code from...

src/arm/disasm-arm.cc

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 83 matching lines @@
  private:
   // Bottleneck functions to print into the out_buffer.
   void PrintChar(const char ch);
   void Print(const char* str);
 
   // Printing of common values.
   void PrintRegister(int reg);
   void PrintSRegister(int reg);
   void PrintDRegister(int reg);
   int FormatVFPRegister(Instr* instr, const char* format);
+  void PrintMovwMovt(Instr* instr);
   int FormatVFPinstruction(Instr* instr, const char* format);
   void PrintCondition(Instr* instr);
   void PrintShiftRm(Instr* instr);
   void PrintShiftImm(Instr* instr);
   void PrintPU(Instr* instr);
   void PrintSoftwareInterrupt(SoftwareInterruptCodes swi);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instr* instr, const char* option);
   int FormatOption(Instr* instr, const char* option);
@@ skipping 254 matching lines @@
   return -1;
 }
 
 
 int Decoder::FormatVFPinstruction(Instr* instr, const char* format) {
     Print(format);
     return 0;
 }
 
 
+// Print the movw or movt instruction.
+void Decoder::PrintMovwMovt(Instr* instr) {
+  int imm = instr->ImmedMovwMovtField();
+  int rd = instr->RdField();
+  PrintRegister(rd);
+  if (instr->Bit(22) == 1) {
+    // Movt instruction.
+    out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,

[Søren Thygesen Gjesse, 2010/06/21 21:39:26]

According to the ARM reference manual the assembler syntax is

  MOVT<c><q> <Rd>, #<imm16>

(without the trailing 0's)

+                                         ", #0x%04x0000", imm);
+  } else {
+    // Movw instruction
+    out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                         ", #0x%04x", imm);
+  }
+}
+
+
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
 // consumed by the caller.)  FormatOption returns the number of
 // characters that were consumed from the formatting string.
 int Decoder::FormatOption(Instr* instr, const char* format) {
   switch (format[0]) {
     case 'a': {  // 'a: accumulate multiplies
       if (instr->Bit(21) == 0) {
         Print("ul");
@@ skipping 35 matching lines @@
       }
       return 1;
     }
     case 'l': {  // 'l: branch and link
       if (instr->HasLink()) {
         Print("l");
       }
       return 1;
     }
     case 'm': {
-      if (format[1] == 'e') {  // 'memop: load/store instructions
+      if ((format[1] == 't') || (format[1] == 'w')) {
+        // 't and 'w: movt/movw instructions.
+        PrintMovwMovt(instr);
+        return 2;
+      }
+      if (format[1] == 'e') {  // 'memop: load/store instructions.
         ASSERT(STRING_STARTS_WITH(format, "memop"));
         if (instr->HasL()) {
           Print("ldr");
         } else if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0)) {
           if (instr->Bits(7, 4) == 0xf) {
             Print("strd");
           } else {
             Print("ldrd");
           }
         } else {
@@ skipping 325 matching lines @@
         break;
       }
       case RSC: {
         Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
         break;
       }
       case TST: {
         if (instr->HasS()) {
           Format(instr, "tst'cond 'rn, 'shift_op");
         } else {
-          Unknown(instr);  // not used by V8
+          Format(instr, "movw'cond 'mw");
         }
         break;
       }
       case TEQ: {
         if (instr->HasS()) {
           Format(instr, "teq'cond 'rn, 'shift_op");
         } else {
           // Other instructions matching this pattern are handled in the
           // miscellaneous instructions part above.
           UNREACHABLE();
         }
         break;
       }
       case CMP: {
         if (instr->HasS()) {
           Format(instr, "cmp'cond 'rn, 'shift_op");
         } else {
-          Unknown(instr);  // not used by V8
+          Format(instr, "movt'cond 'mt");
         }
         break;
       }
       case CMN: {
         if (instr->HasS()) {
           Format(instr, "cmn'cond 'rn, 'shift_op");
         } else {
           // Other instructions matching this pattern are handled in the
           // miscellaneous instructions part above.
           UNREACHABLE();
@@ skipping 565 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     fprintf(f, "%p    %08x      %s\n",
             prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM