| OLD | NEW |
| 1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
| (...skipping 266 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 277 inline int SField() const { return Bit(20); } | 277 inline int SField() const { return Bit(20); } |
| 278 // with register | 278 // with register |
| 279 inline int RmField() const { return Bits(3, 0); } | 279 inline int RmField() const { return Bits(3, 0); } |
| 280 inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); } | 280 inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); } |
| 281 inline int RegShiftField() const { return Bit(4); } | 281 inline int RegShiftField() const { return Bit(4); } |
| 282 inline int RsField() const { return Bits(11, 8); } | 282 inline int RsField() const { return Bits(11, 8); } |
| 283 inline int ShiftAmountField() const { return Bits(11, 7); } | 283 inline int ShiftAmountField() const { return Bits(11, 7); } |
| 284 // with immediate | 284 // with immediate |
| 285 inline int RotateField() const { return Bits(11, 8); } | 285 inline int RotateField() const { return Bits(11, 8); } |
| 286 inline int Immed8Field() const { return Bits(7, 0); } | 286 inline int Immed8Field() const { return Bits(7, 0); } |
| 287 inline int Immed4Field() const { return Bits(19, 16); } |
| 288 inline int ImmedMovwMovtField() const { |
| 289 return Immed4Field() << 12 | Offset12Field(); } |
| 287 | 290 |
| 288 // Fields used in Load/Store instructions | 291 // Fields used in Load/Store instructions |
| 289 inline int PUField() const { return Bits(24, 23); } | 292 inline int PUField() const { return Bits(24, 23); } |
| 290 inline int BField() const { return Bit(22); } | 293 inline int BField() const { return Bit(22); } |
| 291 inline int WField() const { return Bit(21); } | 294 inline int WField() const { return Bit(21); } |
| 292 inline int LField() const { return Bit(20); } | 295 inline int LField() const { return Bit(20); } |
| 293 // with register uses same fields as Data processing instructions above | 296 // with register uses same fields as Data processing instructions above |
| 294 // with immediate | 297 // with immediate |
| 295 inline int Offset12Field() const { return Bits(11, 0); } | 298 inline int Offset12Field() const { return Bits(11, 0); } |
| 296 // multiple | 299 // multiple |
| (...skipping 76 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 373 static int Number(const char* name, bool* is_double); | 376 static int Number(const char* name, bool* is_double); |
| 374 | 377 |
| 375 private: | 378 private: |
| 376 static const char* names_[kNumVFPRegisters]; | 379 static const char* names_[kNumVFPRegisters]; |
| 377 }; | 380 }; |
| 378 | 381 |
| 379 | 382 |
| 380 } } // namespace assembler::arm | 383 } } // namespace assembler::arm |
| 381 | 384 |
| 382 #endif // V8_ARM_CONSTANTS_ARM_H_ | 385 #endif // V8_ARM_CONSTANTS_ARM_H_ |
| OLD | NEW |