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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1795 // Vsrc(15-12) | 1011(11-8) | (offset/4) | 1795 // Vsrc(15-12) | 1011(11-8) | (offset/4) |
1796 ASSERT(CpuFeatures::IsEnabled(VFP3)); | 1796 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
1797 ASSERT(offset % 4 == 0); | 1797 ASSERT(offset % 4 == 0); |
1798 ASSERT((offset / 4) < 256); | 1798 ASSERT((offset / 4) < 256); |
1799 emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 | | 1799 emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 | |
1800 0xB*B8 | ((offset / 4) & 255)); | 1800 0xB*B8 | ((offset / 4) & 255)); |
1801 } | 1801 } |
1802 | 1802 |
1803 | 1803 |
1804 void Assembler::vmov(const DwVfpRegister dst, | 1804 void Assembler::vmov(const DwVfpRegister dst, |
| 1805 const DwVfpRegister src, |
| 1806 const Condition cond) { |
| 1807 // Dd = Dm |
| 1808 // Instruction details available in ARM DDI 0406B, A8-642. |
| 1809 emit(cond | 0xE*B24 | 0xB*B20 | |
| 1810 dst.code()*B12 | 0x5*B9 | B8 | B6 | src.code()); |
| 1811 } |
| 1812 |
| 1813 |
| 1814 void Assembler::vmov(const DwVfpRegister dst, |
1805 const Register src1, | 1815 const Register src1, |
1806 const Register src2, | 1816 const Register src2, |
1807 const Condition cond) { | 1817 const Condition cond) { |
1808 // Dm = <Rt,Rt2>. | 1818 // Dm = <Rt,Rt2>. |
1809 // Instruction details available in ARM DDI 0406A, A8-646. | 1819 // Instruction details available in ARM DDI 0406A, A8-646. |
1810 // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | | 1820 // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | |
1811 // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm | 1821 // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm |
1812 ASSERT(CpuFeatures::IsEnabled(VFP3)); | 1822 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
1813 ASSERT(!src1.is(pc) && !src2.is(pc)); | 1823 ASSERT(!src1.is(pc) && !src2.is(pc)); |
1814 emit(cond | 0xC*B24 | B22 | src2.code()*B16 | | 1824 emit(cond | 0xC*B24 | B22 | src2.code()*B16 | |
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2397 | 2407 |
2398 // Since a constant pool was just emitted, move the check offset forward by | 2408 // Since a constant pool was just emitted, move the check offset forward by |
2399 // the standard interval. | 2409 // the standard interval. |
2400 next_buffer_check_ = pc_offset() + kCheckConstInterval; | 2410 next_buffer_check_ = pc_offset() + kCheckConstInterval; |
2401 } | 2411 } |
2402 | 2412 |
2403 | 2413 |
2404 } } // namespace v8::internal | 2414 } } // namespace v8::internal |
2405 | 2415 |
2406 #endif // V8_TARGET_ARCH_ARM | 2416 #endif // V8_TARGET_ARCH_ARM |
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