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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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103 } | 103 } |
104 | 104 |
105 | 105 |
106 Address* RelocInfo::target_reference_address() { | 106 Address* RelocInfo::target_reference_address() { |
107 ASSERT(rmode_ == EXTERNAL_REFERENCE); | 107 ASSERT(rmode_ == EXTERNAL_REFERENCE); |
108 return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_)); | 108 return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_)); |
109 } | 109 } |
110 | 110 |
111 | 111 |
112 Address RelocInfo::call_address() { | 112 Address RelocInfo::call_address() { |
113 ASSERT(IsCallInstruction()); | 113 ASSERT(IsPatchedReturnSequence()); |
114 // The 2 instructions offset assumes patched return sequence. | 114 // The 2 instructions offset assumes patched return sequence. |
115 ASSERT(IsJSReturn(rmode())); | 115 ASSERT(IsJSReturn(rmode())); |
116 return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize); | 116 return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize); |
117 } | 117 } |
118 | 118 |
119 | 119 |
120 void RelocInfo::set_call_address(Address target) { | 120 void RelocInfo::set_call_address(Address target) { |
121 ASSERT(IsCallInstruction()); | 121 ASSERT(IsPatchedReturnSequence()); |
122 // The 2 instructions offset assumes patched return sequence. | 122 // The 2 instructions offset assumes patched return sequence. |
123 ASSERT(IsJSReturn(rmode())); | 123 ASSERT(IsJSReturn(rmode())); |
124 Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target; | 124 Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target; |
125 } | 125 } |
126 | 126 |
127 | 127 |
128 Object* RelocInfo::call_object() { | 128 Object* RelocInfo::call_object() { |
129 return *call_object_address(); | 129 return *call_object_address(); |
130 } | 130 } |
131 | 131 |
132 | 132 |
133 Object** RelocInfo::call_object_address() { | 133 Object** RelocInfo::call_object_address() { |
134 ASSERT(IsCallInstruction()); | 134 ASSERT(IsPatchedReturnSequence()); |
135 // The 2 instructions offset assumes patched return sequence. | 135 // The 2 instructions offset assumes patched return sequence. |
136 ASSERT(IsJSReturn(rmode())); | 136 ASSERT(IsJSReturn(rmode())); |
137 return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize); | 137 return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize); |
138 } | 138 } |
139 | 139 |
140 | 140 |
141 void RelocInfo::set_call_object(Object* target) { | 141 void RelocInfo::set_call_object(Object* target) { |
142 *call_object_address() = target; | 142 *call_object_address() = target; |
143 } | 143 } |
144 | 144 |
145 | 145 |
146 bool RelocInfo::IsCallInstruction() { | 146 bool RelocInfo::IsPatchedReturnSequence() { |
147 // On ARM a "call instruction" is actually two instructions. | 147 // On ARM a "call instruction" is actually two instructions. |
148 // mov lr, pc | 148 // mov lr, pc |
149 // ldr pc, [pc, #XXX] | 149 // ldr pc, [pc, #XXX] |
150 return (Assembler::instr_at(pc_) == kMovLrPc) | 150 return (Assembler::instr_at(pc_) == kMovLrPc) |
151 && ((Assembler::instr_at(pc_ + Assembler::kInstrSize) & kLdrPCPattern) | 151 && ((Assembler::instr_at(pc_ + Assembler::kInstrSize) & kLdrPCPattern) |
152 == kLdrPCPattern); | 152 == kLdrPCPattern); |
153 } | 153 } |
154 | 154 |
155 | 155 |
156 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { | 156 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { |
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252 // CPU::FlushICache(pc, sizeof(target)); | 252 // CPU::FlushICache(pc, sizeof(target)); |
253 // However, on ARM, no instruction was actually patched by the assignment | 253 // However, on ARM, no instruction was actually patched by the assignment |
254 // above; the target address is not part of an instruction, it is patched in | 254 // above; the target address is not part of an instruction, it is patched in |
255 // the constant pool and is read via a data access; the instruction accessing | 255 // the constant pool and is read via a data access; the instruction accessing |
256 // this address in the constant pool remains unchanged. | 256 // this address in the constant pool remains unchanged. |
257 } | 257 } |
258 | 258 |
259 } } // namespace v8::internal | 259 } } // namespace v8::internal |
260 | 260 |
261 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ | 261 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ |
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