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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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683 void sub(Register dst, Register src1, Register src2, | 683 void sub(Register dst, Register src1, Register src2, |
684 SBit s = LeaveCC, Condition cond = al) { | 684 SBit s = LeaveCC, Condition cond = al) { |
685 sub(dst, src1, Operand(src2), s, cond); | 685 sub(dst, src1, Operand(src2), s, cond); |
686 } | 686 } |
687 | 687 |
688 void rsb(Register dst, Register src1, const Operand& src2, | 688 void rsb(Register dst, Register src1, const Operand& src2, |
689 SBit s = LeaveCC, Condition cond = al); | 689 SBit s = LeaveCC, Condition cond = al); |
690 | 690 |
691 void add(Register dst, Register src1, const Operand& src2, | 691 void add(Register dst, Register src1, const Operand& src2, |
692 SBit s = LeaveCC, Condition cond = al); | 692 SBit s = LeaveCC, Condition cond = al); |
| 693 void add(Register dst, Register src1, Register src2, |
| 694 SBit s = LeaveCC, Condition cond = al) { |
| 695 add(dst, src1, Operand(src2), s, cond); |
| 696 } |
693 | 697 |
694 void adc(Register dst, Register src1, const Operand& src2, | 698 void adc(Register dst, Register src1, const Operand& src2, |
695 SBit s = LeaveCC, Condition cond = al); | 699 SBit s = LeaveCC, Condition cond = al); |
696 | 700 |
697 void sbc(Register dst, Register src1, const Operand& src2, | 701 void sbc(Register dst, Register src1, const Operand& src2, |
698 SBit s = LeaveCC, Condition cond = al); | 702 SBit s = LeaveCC, Condition cond = al); |
699 | 703 |
700 void rsc(Register dst, Register src1, const Operand& src2, | 704 void rsc(Register dst, Register src1, const Operand& src2, |
701 SBit s = LeaveCC, Condition cond = al); | 705 SBit s = LeaveCC, Condition cond = al); |
702 | 706 |
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1147 | 1151 |
1148 friend class RegExpMacroAssemblerARM; | 1152 friend class RegExpMacroAssemblerARM; |
1149 friend class RelocInfo; | 1153 friend class RelocInfo; |
1150 friend class CodePatcher; | 1154 friend class CodePatcher; |
1151 friend class BlockConstPoolScope; | 1155 friend class BlockConstPoolScope; |
1152 }; | 1156 }; |
1153 | 1157 |
1154 } } // namespace v8::internal | 1158 } } // namespace v8::internal |
1155 | 1159 |
1156 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1160 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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