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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1356 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) { | 1356 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) { |
1357 addrmod3(cond | L | B7 | S6 | B4, dst, src); | 1357 addrmod3(cond | L | B7 | S6 | B4, dst, src); |
1358 } | 1358 } |
1359 | 1359 |
1360 | 1360 |
1361 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { | 1361 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { |
1362 addrmod3(cond | L | B7 | S6 | H | B4, dst, src); | 1362 addrmod3(cond | L | B7 | S6 | H | B4, dst, src); |
1363 } | 1363 } |
1364 | 1364 |
1365 | 1365 |
1366 void Assembler::ldrd(Register dst1, | 1366 void Assembler::ldrd(Register dst1, Register dst2, |
1367 Register dst2, | |
1368 const MemOperand& src, Condition cond) { | 1367 const MemOperand& src, Condition cond) { |
| 1368 ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
1369 ASSERT(src.rm().is(no_reg)); | 1369 ASSERT(src.rm().is(no_reg)); |
1370 ASSERT(!dst1.is(lr)); // r14. | 1370 ASSERT(!dst1.is(lr)); // r14. |
1371 ASSERT_EQ(0, dst1.code() % 2); | 1371 ASSERT_EQ(0, dst1.code() % 2); |
1372 ASSERT_EQ(dst1.code() + 1, dst2.code()); | 1372 ASSERT_EQ(dst1.code() + 1, dst2.code()); |
1373 #ifdef CAN_USE_ARMV7_INSTRUCTIONS | |
1374 addrmod3(cond | B7 | B6 | B4, dst1, src); | 1373 addrmod3(cond | B7 | B6 | B4, dst1, src); |
1375 #else | |
1376 // Generate two ldr instructions if ldrd is not available. | |
1377 MemOperand src2(src); | |
1378 src2.set_offset(src2.offset() + 4); | |
1379 if (dst1.is(src.rn())) { | |
1380 ldr(dst2, src2, cond); | |
1381 ldr(dst1, src, cond); | |
1382 } else { | |
1383 ldr(dst1, src, cond); | |
1384 ldr(dst2, src2, cond); | |
1385 } | |
1386 #endif | |
1387 } | 1374 } |
1388 | 1375 |
1389 | 1376 |
1390 void Assembler::strd(Register src1, | 1377 void Assembler::strd(Register src1, Register src2, |
1391 Register src2, | |
1392 const MemOperand& dst, Condition cond) { | 1378 const MemOperand& dst, Condition cond) { |
1393 ASSERT(dst.rm().is(no_reg)); | 1379 ASSERT(dst.rm().is(no_reg)); |
1394 ASSERT(!src1.is(lr)); // r14. | 1380 ASSERT(!src1.is(lr)); // r14. |
1395 ASSERT_EQ(0, src1.code() % 2); | 1381 ASSERT_EQ(0, src1.code() % 2); |
1396 ASSERT_EQ(src1.code() + 1, src2.code()); | 1382 ASSERT_EQ(src1.code() + 1, src2.code()); |
1397 #ifdef CAN_USE_ARMV7_INSTRUCTIONS | 1383 ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
1398 addrmod3(cond | B7 | B6 | B5 | B4, src1, dst); | 1384 addrmod3(cond | B7 | B6 | B5 | B4, src1, dst); |
1399 #else | |
1400 // Generate two str instructions if strd is not available. | |
1401 MemOperand dst2(dst); | |
1402 dst2.set_offset(dst2.offset() + 4); | |
1403 str(src1, dst, cond); | |
1404 str(src2, dst2, cond); | |
1405 #endif | |
1406 } | 1385 } |
1407 | 1386 |
1408 // Load/Store multiple instructions. | 1387 // Load/Store multiple instructions. |
1409 void Assembler::ldm(BlockAddrMode am, | 1388 void Assembler::ldm(BlockAddrMode am, |
1410 Register base, | 1389 Register base, |
1411 RegList dst, | 1390 RegList dst, |
1412 Condition cond) { | 1391 Condition cond) { |
1413 // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable. | 1392 // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable. |
1414 ASSERT(base.is(sp) || (dst & sp.bit()) == 0); | 1393 ASSERT(base.is(sp) || (dst & sp.bit()) == 0); |
1415 | 1394 |
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2228 | 2207 |
2229 // Since a constant pool was just emitted, move the check offset forward by | 2208 // Since a constant pool was just emitted, move the check offset forward by |
2230 // the standard interval. | 2209 // the standard interval. |
2231 next_buffer_check_ = pc_offset() + kCheckConstInterval; | 2210 next_buffer_check_ = pc_offset() + kCheckConstInterval; |
2232 } | 2211 } |
2233 | 2212 |
2234 | 2213 |
2235 } } // namespace v8::internal | 2214 } } // namespace v8::internal |
2236 | 2215 |
2237 #endif // V8_TARGET_ARCH_ARM | 2216 #endif // V8_TARGET_ARCH_ARM |
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