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Unified Diff: src/arm/assembler-arm.cc

Issue 2122021: Make ldrd and strd instructions take two register arguments (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 7 months ago
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Index: src/arm/assembler-arm.cc
===================================================================
--- src/arm/assembler-arm.cc (revision 4722)
+++ src/arm/assembler-arm.cc (working copy)
@@ -1363,39 +1363,45 @@
}
-void Assembler::ldrd(Register dst, const MemOperand& src, Condition cond) {
+void Assembler::ldrd(Register dst1,
+ Register dst2,
+ const MemOperand& src, Condition cond) {
ASSERT(src.rm().is(no_reg));
+ ASSERT(!dst1.is(lr)); // r14.
+ ASSERT_EQ(0, dst1.code() % 2);
+ ASSERT_EQ(dst1.code() + 1, dst2.code());
#ifdef CAN_USE_ARMV7_INSTRUCTIONS
- addrmod3(cond | B7 | B6 | B4, dst, src);
+ addrmod3(cond | B7 | B6 | B4, dst1, src);
#else
// Generate two ldr instructions if ldrd is not available.
- MemOperand src1(src);
- src1.set_offset(src1.offset() + 4);
- Register dst1(dst);
- dst1.set_code(dst1.code() + 1);
- if (dst.is(src.rn())) {
- ldr(dst1, src1, cond);
- ldr(dst, src, cond);
+ MemOperand src2(src);
+ src2.set_offset(src2.offset() + 4);
+ if (dst1.is(src.rn())) {
+ ldr(dst2, src2, cond);
+ ldr(dst1, src, cond);
} else {
- ldr(dst, src, cond);
- ldr(dst1, src1, cond);
+ ldr(dst1, src, cond);
+ ldr(dst2, src2, cond);
}
#endif
}
-void Assembler::strd(Register src, const MemOperand& dst, Condition cond) {
+void Assembler::strd(Register src1,
+ Register src2,
+ const MemOperand& dst, Condition cond) {
ASSERT(dst.rm().is(no_reg));
+ ASSERT(!src1.is(lr)); // r14.
+ ASSERT_EQ(0, src1.code() % 2);
+ ASSERT_EQ(src1.code() + 1, src2.code());
#ifdef CAN_USE_ARMV7_INSTRUCTIONS
- addrmod3(cond | B7 | B6 | B5 | B4, src, dst);
+ addrmod3(cond | B7 | B6 | B5 | B4, src1, dst);
#else
// Generate two str instructions if strd is not available.
- MemOperand dst1(dst);
- dst1.set_offset(dst1.offset() + 4);
- Register src1(src);
- src1.set_code(src1.code() + 1);
- str(src, dst, cond);
- str(src1, dst1, cond);
+ MemOperand dst2(dst);
+ dst2.set_offset(dst2.offset() + 4);
+ str(src1, dst, cond);
+ str(src2, dst2, cond);
#endif
}
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