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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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73 bool is(Register reg) const { return code_ == reg.code_; } | 73 bool is(Register reg) const { return code_ == reg.code_; } |
74 int code() const { | 74 int code() const { |
75 ASSERT(is_valid()); | 75 ASSERT(is_valid()); |
76 return code_; | 76 return code_; |
77 } | 77 } |
78 int bit() const { | 78 int bit() const { |
79 ASSERT(is_valid()); | 79 ASSERT(is_valid()); |
80 return 1 << code_; | 80 return 1 << code_; |
81 } | 81 } |
82 | 82 |
| 83 void set_code(int code) { |
| 84 code_ = code; |
| 85 ASSERT(is_valid()); |
| 86 } |
| 87 |
83 // Unfortunately we can't make this private in a struct. | 88 // Unfortunately we can't make this private in a struct. |
84 int code_; | 89 int code_; |
85 }; | 90 }; |
86 | 91 |
87 const Register no_reg = { -1 }; | 92 const Register no_reg = { -1 }; |
88 | 93 |
89 const Register r0 = { 0 }; | 94 const Register r0 = { 0 }; |
90 const Register r1 = { 1 }; | 95 const Register r1 = { 1 }; |
91 const Register r2 = { 2 }; | 96 const Register r2 = { 2 }; |
92 const Register r3 = { 3 }; | 97 const Register r3 = { 3 }; |
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451 void set_offset(int32_t offset) { | 456 void set_offset(int32_t offset) { |
452 ASSERT(rm_.is(no_reg)); | 457 ASSERT(rm_.is(no_reg)); |
453 offset_ = offset; | 458 offset_ = offset; |
454 } | 459 } |
455 | 460 |
456 uint32_t offset() { | 461 uint32_t offset() { |
457 ASSERT(rm_.is(no_reg)); | 462 ASSERT(rm_.is(no_reg)); |
458 return offset_; | 463 return offset_; |
459 } | 464 } |
460 | 465 |
461 Register rm() const {return rm_;} | 466 Register rn() const { return rn_; } |
| 467 Register rm() const { return rm_; } |
462 | 468 |
463 private: | 469 private: |
464 Register rn_; // base | 470 Register rn_; // base |
465 Register rm_; // register offset | 471 Register rm_; // register offset |
466 int32_t offset_; // valid if rm_ == no_reg | 472 int32_t offset_; // valid if rm_ == no_reg |
467 ShiftOp shift_op_; | 473 ShiftOp shift_op_; |
468 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg | 474 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg |
469 AddrMode am_; // bits P, U, and W | 475 AddrMode am_; // bits P, U, and W |
470 | 476 |
471 friend class Assembler; | 477 friend class Assembler; |
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767 void strh(Register src, const MemOperand& dst, Condition cond = al); | 773 void strh(Register src, const MemOperand& dst, Condition cond = al); |
768 void ldrsb(Register dst, const MemOperand& src, Condition cond = al); | 774 void ldrsb(Register dst, const MemOperand& src, Condition cond = al); |
769 void ldrsh(Register dst, const MemOperand& src, Condition cond = al); | 775 void ldrsh(Register dst, const MemOperand& src, Condition cond = al); |
770 void ldrd(Register dst, const MemOperand& src, Condition cond = al); | 776 void ldrd(Register dst, const MemOperand& src, Condition cond = al); |
771 void strd(Register src, const MemOperand& dst, Condition cond = al); | 777 void strd(Register src, const MemOperand& dst, Condition cond = al); |
772 | 778 |
773 // Load/Store multiple instructions | 779 // Load/Store multiple instructions |
774 void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al); | 780 void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al); |
775 void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al); | 781 void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al); |
776 | 782 |
777 // Semaphore instructions | |
778 void swp(Register dst, Register src, Register base, Condition cond = al); | |
779 void swpb(Register dst, Register src, Register base, Condition cond = al); | |
780 | |
781 // Exception-generating instructions and debugging support | 783 // Exception-generating instructions and debugging support |
782 void stop(const char* msg); | 784 void stop(const char* msg); |
783 | 785 |
784 void bkpt(uint32_t imm16); // v5 and above | 786 void bkpt(uint32_t imm16); // v5 and above |
785 void swi(uint32_t imm24, Condition cond = al); | 787 void swi(uint32_t imm24, Condition cond = al); |
786 | 788 |
787 // Coprocessor instructions | 789 // Coprocessor instructions |
788 | 790 |
789 void cdp(Coprocessor coproc, int opcode_1, | 791 void cdp(Coprocessor coproc, int opcode_1, |
790 CRegister crd, CRegister crn, CRegister crm, | 792 CRegister crd, CRegister crn, CRegister crm, |
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917 } | 919 } |
918 | 920 |
919 void pop(Register dst, Condition cond = al) { | 921 void pop(Register dst, Condition cond = al) { |
920 ldr(dst, MemOperand(sp, 4, PostIndex), cond); | 922 ldr(dst, MemOperand(sp, 4, PostIndex), cond); |
921 } | 923 } |
922 | 924 |
923 void pop() { | 925 void pop() { |
924 add(sp, sp, Operand(kPointerSize)); | 926 add(sp, sp, Operand(kPointerSize)); |
925 } | 927 } |
926 | 928 |
927 // Load effective address of memory operand x into register dst | |
928 void lea(Register dst, const MemOperand& x, | |
929 SBit s = LeaveCC, Condition cond = al); | |
930 | |
931 // Jump unconditionally to given label. | 929 // Jump unconditionally to given label. |
932 void jmp(Label* L) { b(L, al); } | 930 void jmp(Label* L) { b(L, al); } |
933 | 931 |
934 // Check the code size generated from label to here. | 932 // Check the code size generated from label to here. |
935 int InstructionsGeneratedSince(Label* l) { | 933 int InstructionsGeneratedSince(Label* l) { |
936 return (pc_offset() - l->pos()) / kInstrSize; | 934 return (pc_offset() - l->pos()) / kInstrSize; |
937 } | 935 } |
938 | 936 |
939 // Check whether an immediate fits an addressing mode 1 instruction. | 937 // Check whether an immediate fits an addressing mode 1 instruction. |
940 bool ImmediateFitsAddrMode1Instruction(int32_t imm32); | 938 bool ImmediateFitsAddrMode1Instruction(int32_t imm32); |
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969 void RecordComment(const char* msg); | 967 void RecordComment(const char* msg); |
970 | 968 |
971 void RecordPosition(int pos); | 969 void RecordPosition(int pos); |
972 void RecordStatementPosition(int pos); | 970 void RecordStatementPosition(int pos); |
973 void WriteRecordedPositions(); | 971 void WriteRecordedPositions(); |
974 | 972 |
975 int pc_offset() const { return pc_ - buffer_; } | 973 int pc_offset() const { return pc_ - buffer_; } |
976 int current_position() const { return current_position_; } | 974 int current_position() const { return current_position_; } |
977 int current_statement_position() const { return current_statement_position_; } | 975 int current_statement_position() const { return current_statement_position_; } |
978 | 976 |
| 977 bool can_peephole_optimize(int instructions) { |
| 978 if (!FLAG_peephole_optimization) return false; |
| 979 if (last_bound_pos_ > pc_offset() - instructions * kInstrSize) return false; |
| 980 return reloc_info_writer.last_pc() <= pc_ - instructions * kInstrSize; |
| 981 } |
| 982 |
979 // Read/patch instructions | 983 // Read/patch instructions |
980 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); } | 984 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); } |
981 static void instr_at_put(byte* pc, Instr instr) { | 985 static void instr_at_put(byte* pc, Instr instr) { |
982 *reinterpret_cast<Instr*>(pc) = instr; | 986 *reinterpret_cast<Instr*>(pc) = instr; |
983 } | 987 } |
984 static bool IsNop(Instr instr, int type = 0); | 988 static bool IsNop(Instr instr, int type = 0); |
985 static bool IsBranch(Instr instr); | 989 static bool IsBranch(Instr instr); |
986 static int GetBranchOffset(Instr instr); | 990 static int GetBranchOffset(Instr instr); |
987 static bool IsLdrRegisterImmediate(Instr instr); | 991 static bool IsLdrRegisterImmediate(Instr instr); |
988 static int GetLdrRegisterImmediateOffset(Instr instr); | 992 static int GetLdrRegisterImmediateOffset(Instr instr); |
989 static Instr SetLdrRegisterImmediateOffset(Instr instr, int offset); | 993 static Instr SetLdrRegisterImmediateOffset(Instr instr, int offset); |
| 994 static Register GetRd(Instr instr); |
| 995 static bool IsPush(Instr instr); |
| 996 static bool IsPop(Instr instr); |
| 997 static bool IsStrRegFpOffset(Instr instr); |
| 998 static bool IsLdrRegFpOffset(Instr instr); |
| 999 static bool IsStrRegFpNegOffset(Instr instr); |
| 1000 static bool IsLdrRegFpNegOffset(Instr instr); |
990 | 1001 |
991 | 1002 |
992 protected: | 1003 protected: |
993 int buffer_space() const { return reloc_info_writer.pos() - pc_; } | 1004 int buffer_space() const { return reloc_info_writer.pos() - pc_; } |
994 | 1005 |
995 // Read/patch instructions | 1006 // Read/patch instructions |
996 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); } | 1007 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); } |
997 void instr_at_put(int pos, Instr instr) { | 1008 void instr_at_put(int pos, Instr instr) { |
998 *reinterpret_cast<Instr*>(buffer_ + pos) = instr; | 1009 *reinterpret_cast<Instr*>(buffer_ + pos) = instr; |
999 } | 1010 } |
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1121 | 1132 |
1122 friend class RegExpMacroAssemblerARM; | 1133 friend class RegExpMacroAssemblerARM; |
1123 friend class RelocInfo; | 1134 friend class RelocInfo; |
1124 friend class CodePatcher; | 1135 friend class CodePatcher; |
1125 friend class BlockConstPoolScope; | 1136 friend class BlockConstPoolScope; |
1126 }; | 1137 }; |
1127 | 1138 |
1128 } } // namespace v8::internal | 1139 } } // namespace v8::internal |
1129 | 1140 |
1130 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1141 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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