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Issue 2080017: Remove the fledgling Thumb2 support since we are concentrating... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 10 years, 7 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
6 // are met:
7 //
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
10 //
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
14 // distribution.
15 //
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
19 //
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
32
33 // The original source code covered by the above license above has been
34 // modified significantly by Google Inc.
35 // Copyright 2010 the V8 project authors. All rights reserved.
36
37 #include "v8.h"
38
39 #if defined(V8_TARGET_ARCH_ARM) && defined(V8_ARM_VARIANT_THUMB)
40
41 #include "arm/assembler-thumb2-inl.h"
42 #include "serialize.h"
43
44 namespace v8 {
45 namespace internal {
46
47 // Safe default is no features.
48 unsigned CpuFeatures::supported_ = 0;
49 unsigned CpuFeatures::enabled_ = 0;
50 unsigned CpuFeatures::found_by_runtime_probing_ = 0;
51
52 void CpuFeatures::Probe() {
53 // If the compiler is allowed to use vfp then we can use vfp too in our
54 // code generation.
55 #if !defined(__arm__)
56 // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is enabled.
57 if (FLAG_enable_vfp3) {
58 supported_ |= 1u << VFP3;
59 }
60 // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled
61 if (FLAG_enable_armv7) {
62 supported_ |= 1u << ARMv7;
63 }
64 #else
65 if (Serializer::enabled()) {
66 supported_ |= OS::CpuFeaturesImpliedByPlatform();
67 return; // No features if we might serialize.
68 }
69
70 if (OS::ArmCpuHasFeature(VFP3)) {
71 // This implementation also sets the VFP flags if
72 // runtime detection of VFP returns true.
73 supported_ |= 1u << VFP3;
74 found_by_runtime_probing_ |= 1u << VFP3;
75 }
76
77 if (OS::ArmCpuHasFeature(ARMv7)) {
78 supported_ |= 1u << ARMv7;
79 found_by_runtime_probing_ |= 1u << ARMv7;
80 }
81 #endif
82 }
83
84
85 // -----------------------------------------------------------------------------
86 // Implementation of Register and CRegister
87
88 Register no_reg = { -1 };
89
90 Register r0 = { 0 };
91 Register r1 = { 1 };
92 Register r2 = { 2 };
93 Register r3 = { 3 };
94 Register r4 = { 4 };
95 Register r5 = { 5 };
96 Register r6 = { 6 };
97 Register r7 = { 7 };
98 Register r8 = { 8 }; // Used as context register.
99 Register r9 = { 9 };
100 Register r10 = { 10 }; // Used as roots register.
101 Register fp = { 11 };
102 Register ip = { 12 };
103 Register sp = { 13 };
104 Register lr = { 14 };
105 Register pc = { 15 };
106
107
108 CRegister no_creg = { -1 };
109
110 CRegister cr0 = { 0 };
111 CRegister cr1 = { 1 };
112 CRegister cr2 = { 2 };
113 CRegister cr3 = { 3 };
114 CRegister cr4 = { 4 };
115 CRegister cr5 = { 5 };
116 CRegister cr6 = { 6 };
117 CRegister cr7 = { 7 };
118 CRegister cr8 = { 8 };
119 CRegister cr9 = { 9 };
120 CRegister cr10 = { 10 };
121 CRegister cr11 = { 11 };
122 CRegister cr12 = { 12 };
123 CRegister cr13 = { 13 };
124 CRegister cr14 = { 14 };
125 CRegister cr15 = { 15 };
126
127 // Support for the VFP registers s0 to s31 (d0 to d15).
128 // Note that "sN:sM" is the same as "dN/2".
129 SwVfpRegister s0 = { 0 };
130 SwVfpRegister s1 = { 1 };
131 SwVfpRegister s2 = { 2 };
132 SwVfpRegister s3 = { 3 };
133 SwVfpRegister s4 = { 4 };
134 SwVfpRegister s5 = { 5 };
135 SwVfpRegister s6 = { 6 };
136 SwVfpRegister s7 = { 7 };
137 SwVfpRegister s8 = { 8 };
138 SwVfpRegister s9 = { 9 };
139 SwVfpRegister s10 = { 10 };
140 SwVfpRegister s11 = { 11 };
141 SwVfpRegister s12 = { 12 };
142 SwVfpRegister s13 = { 13 };
143 SwVfpRegister s14 = { 14 };
144 SwVfpRegister s15 = { 15 };
145 SwVfpRegister s16 = { 16 };
146 SwVfpRegister s17 = { 17 };
147 SwVfpRegister s18 = { 18 };
148 SwVfpRegister s19 = { 19 };
149 SwVfpRegister s20 = { 20 };
150 SwVfpRegister s21 = { 21 };
151 SwVfpRegister s22 = { 22 };
152 SwVfpRegister s23 = { 23 };
153 SwVfpRegister s24 = { 24 };
154 SwVfpRegister s25 = { 25 };
155 SwVfpRegister s26 = { 26 };
156 SwVfpRegister s27 = { 27 };
157 SwVfpRegister s28 = { 28 };
158 SwVfpRegister s29 = { 29 };
159 SwVfpRegister s30 = { 30 };
160 SwVfpRegister s31 = { 31 };
161
162 DwVfpRegister d0 = { 0 };
163 DwVfpRegister d1 = { 1 };
164 DwVfpRegister d2 = { 2 };
165 DwVfpRegister d3 = { 3 };
166 DwVfpRegister d4 = { 4 };
167 DwVfpRegister d5 = { 5 };
168 DwVfpRegister d6 = { 6 };
169 DwVfpRegister d7 = { 7 };
170 DwVfpRegister d8 = { 8 };
171 DwVfpRegister d9 = { 9 };
172 DwVfpRegister d10 = { 10 };
173 DwVfpRegister d11 = { 11 };
174 DwVfpRegister d12 = { 12 };
175 DwVfpRegister d13 = { 13 };
176 DwVfpRegister d14 = { 14 };
177 DwVfpRegister d15 = { 15 };
178
179 // -----------------------------------------------------------------------------
180 // Implementation of RelocInfo
181
182 const int RelocInfo::kApplyMask = 0;
183
184
185 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
186 // Patch the code at the current address with the supplied instructions.
187 Instr* pc = reinterpret_cast<Instr*>(pc_);
188 Instr* instr = reinterpret_cast<Instr*>(instructions);
189 for (int i = 0; i < instruction_count; i++) {
190 *(pc + i) = *(instr + i);
191 }
192
193 // Indicate that code has changed.
194 CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize);
195 }
196
197
198 // Patch the code at the current PC with a call to the target address.
199 // Additional guard instructions can be added if required.
200 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
201 // Patch the code at the current address with a call to the target.
202 UNIMPLEMENTED();
203 }
204
205
206 // -----------------------------------------------------------------------------
207 // Implementation of Operand and MemOperand
208 // See assembler-thumb2-inl.h for inlined constructors
209
210 Operand::Operand(Handle<Object> handle) {
211 rm_ = no_reg;
212 // Verify all Objects referred by code are NOT in new space.
213 Object* obj = *handle;
214 ASSERT(!Heap::InNewSpace(obj));
215 if (obj->IsHeapObject()) {
216 imm32_ = reinterpret_cast<intptr_t>(handle.location());
217 rmode_ = RelocInfo::EMBEDDED_OBJECT;
218 } else {
219 // no relocation needed
220 imm32_ = reinterpret_cast<intptr_t>(obj);
221 rmode_ = RelocInfo::NONE;
222 }
223 }
224
225
226 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
227 ASSERT(is_uint5(shift_imm));
228 ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it
229 rm_ = rm;
230 rs_ = no_reg;
231 shift_op_ = shift_op;
232 shift_imm_ = shift_imm & 31;
233 if (shift_op == RRX) {
234 // encoded as ROR with shift_imm == 0
235 ASSERT(shift_imm == 0);
236 shift_op_ = ROR;
237 shift_imm_ = 0;
238 }
239 }
240
241
242 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
243 ASSERT(shift_op != RRX);
244 rm_ = rm;
245 rs_ = no_reg;
246 shift_op_ = shift_op;
247 rs_ = rs;
248 }
249
250
251 MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) {
252 rn_ = rn;
253 rm_ = no_reg;
254 offset_ = offset;
255 am_ = am;
256 }
257
258 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) {
259 rn_ = rn;
260 rm_ = rm;
261 shift_op_ = LSL;
262 shift_imm_ = 0;
263 am_ = am;
264 }
265
266
267 MemOperand::MemOperand(Register rn, Register rm,
268 ShiftOp shift_op, int shift_imm, AddrMode am) {
269 ASSERT(is_uint5(shift_imm));
270 rn_ = rn;
271 rm_ = rm;
272 shift_op_ = shift_op;
273 shift_imm_ = shift_imm & 31;
274 am_ = am;
275 }
276
277
278 // -----------------------------------------------------------------------------
279 // Implementation of Assembler.
280
281 // Instruction encoding bits.
282 enum {
283 H = 1 << 5, // halfword (or byte)
284 S6 = 1 << 6, // signed (or unsigned)
285 L = 1 << 20, // load (or store)
286 S = 1 << 20, // set condition code (or leave unchanged)
287 W = 1 << 21, // writeback base register (or leave unchanged)
288 A = 1 << 21, // accumulate in multiply instruction (or not)
289 B = 1 << 22, // unsigned byte (or word)
290 N = 1 << 22, // long (or short)
291 U = 1 << 23, // positive (or negative) offset/index
292 P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing)
293 I = 1 << 25, // immediate shifter operand (or not)
294
295 B4 = 1 << 4,
296 B5 = 1 << 5,
297 B6 = 1 << 6,
298 B7 = 1 << 7,
299 B8 = 1 << 8,
300 B9 = 1 << 9,
301 B12 = 1 << 12,
302 B16 = 1 << 16,
303 B18 = 1 << 18,
304 B19 = 1 << 19,
305 B20 = 1 << 20,
306 B21 = 1 << 21,
307 B22 = 1 << 22,
308 B23 = 1 << 23,
309 B24 = 1 << 24,
310 B25 = 1 << 25,
311 B26 = 1 << 26,
312 B27 = 1 << 27,
313
314 // Instruction bit masks.
315 RdMask = 15 << 12, // in str instruction
316 CondMask = 15 << 28,
317 CoprocessorMask = 15 << 8,
318 OpCodeMask = 15 << 21, // in data-processing instructions
319 Imm24Mask = (1 << 24) - 1,
320 Off12Mask = (1 << 12) - 1,
321 // Reserved condition.
322 nv = 15 << 28
323 };
324
325
326 // add(sp, sp, 4) instruction (aka Pop())
327 static const Instr kPopInstruction =
328 al | 4 * B21 | 4 | LeaveCC | I | sp.code() * B16 | sp.code() * B12;
329 // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
330 // register r is not encoded.
331 static const Instr kPushRegPattern =
332 al | B26 | 4 | NegPreIndex | sp.code() * B16;
333 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
334 // register r is not encoded.
335 static const Instr kPopRegPattern =
336 al | B26 | L | 4 | PostIndex | sp.code() * B16;
337 // mov lr, pc
338 const Instr kMovLrPc = al | 13*B21 | pc.code() | lr.code() * B12;
339 // ldr pc, [pc, #XXX]
340 const Instr kLdrPCPattern = al | B26 | L | pc.code() * B16;
341
342 // Spare buffer.
343 static const int kMinimalBufferSize = 4*KB;
344 static byte* spare_buffer_ = NULL;
345
346 Assembler::Assembler(void* buffer, int buffer_size) {
347 if (buffer == NULL) {
348 // Do our own buffer management.
349 if (buffer_size <= kMinimalBufferSize) {
350 buffer_size = kMinimalBufferSize;
351
352 if (spare_buffer_ != NULL) {
353 buffer = spare_buffer_;
354 spare_buffer_ = NULL;
355 }
356 }
357 if (buffer == NULL) {
358 buffer_ = NewArray<byte>(buffer_size);
359 } else {
360 buffer_ = static_cast<byte*>(buffer);
361 }
362 buffer_size_ = buffer_size;
363 own_buffer_ = true;
364
365 } else {
366 // Use externally provided buffer instead.
367 ASSERT(buffer_size > 0);
368 buffer_ = static_cast<byte*>(buffer);
369 buffer_size_ = buffer_size;
370 own_buffer_ = false;
371 }
372
373 // Setup buffer pointers.
374 ASSERT(buffer_ != NULL);
375 pc_ = buffer_;
376 reloc_info_writer.Reposition(buffer_ + buffer_size, pc_);
377 num_prinfo_ = 0;
378 next_buffer_check_ = 0;
379 no_const_pool_before_ = 0;
380 last_const_pool_end_ = 0;
381 last_bound_pos_ = 0;
382 current_statement_position_ = RelocInfo::kNoPosition;
383 current_position_ = RelocInfo::kNoPosition;
384 written_statement_position_ = current_statement_position_;
385 written_position_ = current_position_;
386 }
387
388
389 Assembler::~Assembler() {
390 if (own_buffer_) {
391 if (spare_buffer_ == NULL && buffer_size_ == kMinimalBufferSize) {
392 spare_buffer_ = buffer_;
393 } else {
394 DeleteArray(buffer_);
395 }
396 }
397 }
398
399
400 void Assembler::GetCode(CodeDesc* desc) {
401 // Emit constant pool if necessary.
402 CheckConstPool(true, false);
403 ASSERT(num_prinfo_ == 0);
404
405 // Setup code descriptor.
406 desc->buffer = buffer_;
407 desc->buffer_size = buffer_size_;
408 desc->instr_size = pc_offset();
409 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
410 }
411
412
413 void Assembler::Align(int m) {
414 ASSERT(m >= 4 && IsPowerOf2(m));
415 while ((pc_offset() & (m - 1)) != 0) {
416 nop();
417 }
418 }
419
420
421 // Labels refer to positions in the (to be) generated code.
422 // There are bound, linked, and unused labels.
423 //
424 // Bound labels refer to known positions in the already
425 // generated code. pos() is the position the label refers to.
426 //
427 // Linked labels refer to unknown positions in the code
428 // to be generated; pos() is the position of the last
429 // instruction using the label.
430
431
432 // The link chain is terminated by a negative code position (must be aligned)
433 const int kEndOfChain = -4;
434
435
436 int Assembler::target_at(int pos) {
437 Instr instr = instr_at(pos);
438 if ((instr & ~Imm24Mask) == 0) {
439 // Emitted label constant, not part of a branch.
440 return instr - (Code::kHeaderSize - kHeapObjectTag);
441 }
442 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
443 int imm26 = ((instr & Imm24Mask) << 8) >> 6;
444 if ((instr & CondMask) == nv && (instr & B24) != 0)
445 // blx uses bit 24 to encode bit 2 of imm26
446 imm26 += 2;
447
448 return pos + kPcLoadDelta + imm26;
449 }
450
451
452 void Assembler::target_at_put(int pos, int target_pos) {
453 Instr instr = instr_at(pos);
454 if ((instr & ~Imm24Mask) == 0) {
455 ASSERT(target_pos == kEndOfChain || target_pos >= 0);
456 // Emitted label constant, not part of a branch.
457 // Make label relative to Code* of generated Code object.
458 instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
459 return;
460 }
461 int imm26 = target_pos - (pos + kPcLoadDelta);
462 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
463 if ((instr & CondMask) == nv) {
464 // blx uses bit 24 to encode bit 2 of imm26
465 ASSERT((imm26 & 1) == 0);
466 instr = (instr & ~(B24 | Imm24Mask)) | ((imm26 & 2) >> 1)*B24;
467 } else {
468 ASSERT((imm26 & 3) == 0);
469 instr &= ~Imm24Mask;
470 }
471 int imm24 = imm26 >> 2;
472 ASSERT(is_int24(imm24));
473 instr_at_put(pos, instr | (imm24 & Imm24Mask));
474 }
475
476
477 void Assembler::print(Label* L) {
478 if (L->is_unused()) {
479 PrintF("unused label\n");
480 } else if (L->is_bound()) {
481 PrintF("bound label to %d\n", L->pos());
482 } else if (L->is_linked()) {
483 Label l = *L;
484 PrintF("unbound label");
485 while (l.is_linked()) {
486 PrintF("@ %d ", l.pos());
487 Instr instr = instr_at(l.pos());
488 if ((instr & ~Imm24Mask) == 0) {
489 PrintF("value\n");
490 } else {
491 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx
492 int cond = instr & CondMask;
493 const char* b;
494 const char* c;
495 if (cond == nv) {
496 b = "blx";
497 c = "";
498 } else {
499 if ((instr & B24) != 0)
500 b = "bl";
501 else
502 b = "b";
503
504 switch (cond) {
505 case eq: c = "eq"; break;
506 case ne: c = "ne"; break;
507 case hs: c = "hs"; break;
508 case lo: c = "lo"; break;
509 case mi: c = "mi"; break;
510 case pl: c = "pl"; break;
511 case vs: c = "vs"; break;
512 case vc: c = "vc"; break;
513 case hi: c = "hi"; break;
514 case ls: c = "ls"; break;
515 case ge: c = "ge"; break;
516 case lt: c = "lt"; break;
517 case gt: c = "gt"; break;
518 case le: c = "le"; break;
519 case al: c = ""; break;
520 default:
521 c = "";
522 UNREACHABLE();
523 }
524 }
525 PrintF("%s%s\n", b, c);
526 }
527 next(&l);
528 }
529 } else {
530 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
531 }
532 }
533
534
535 void Assembler::bind_to(Label* L, int pos) {
536 ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position
537 while (L->is_linked()) {
538 int fixup_pos = L->pos();
539 next(L); // call next before overwriting link with target at fixup_pos
540 target_at_put(fixup_pos, pos);
541 }
542 L->bind_to(pos);
543
544 // Keep track of the last bound label so we don't eliminate any instructions
545 // before a bound label.
546 if (pos > last_bound_pos_)
547 last_bound_pos_ = pos;
548 }
549
550
551 void Assembler::link_to(Label* L, Label* appendix) {
552 if (appendix->is_linked()) {
553 if (L->is_linked()) {
554 // Append appendix to L's list.
555 int fixup_pos;
556 int link = L->pos();
557 do {
558 fixup_pos = link;
559 link = target_at(fixup_pos);
560 } while (link > 0);
561 ASSERT(link == kEndOfChain);
562 target_at_put(fixup_pos, appendix->pos());
563 } else {
564 // L is empty, simply use appendix.
565 *L = *appendix;
566 }
567 }
568 appendix->Unuse(); // appendix should not be used anymore
569 }
570
571
572 void Assembler::bind(Label* L) {
573 ASSERT(!L->is_bound()); // label can only be bound once
574 bind_to(L, pc_offset());
575 }
576
577
578 void Assembler::next(Label* L) {
579 ASSERT(L->is_linked());
580 int link = target_at(L->pos());
581 if (link > 0) {
582 L->link_to(link);
583 } else {
584 ASSERT(link == kEndOfChain);
585 L->Unuse();
586 }
587 }
588
589
590 // Low-level code emission routines depending on the addressing mode.
591 static bool fits_shifter(uint32_t imm32,
592 uint32_t* rotate_imm,
593 uint32_t* immed_8,
594 Instr* instr) {
595 // imm32 must be unsigned.
596 for (int rot = 0; rot < 16; rot++) {
597 uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot));
598 if ((imm8 <= 0xff)) {
599 *rotate_imm = rot;
600 *immed_8 = imm8;
601 return true;
602 }
603 }
604 // If the opcode is mov or mvn and if ~imm32 fits, change the opcode.
605 if (instr != NULL && (*instr & 0xd*B21) == 0xd*B21) {
606 if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {
607 *instr ^= 0x2*B21;
608 return true;
609 }
610 }
611 return false;
612 }
613
614
615 // We have to use the temporary register for things that can be relocated even
616 // if they can be encoded in the ARM's 12 bits of immediate-offset instruction
617 // space. There is no guarantee that the relocated location can be similarly
618 // encoded.
619 static bool MustUseIp(RelocInfo::Mode rmode) {
620 if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
621 #ifdef DEBUG
622 if (!Serializer::enabled()) {
623 Serializer::TooLateToEnableNow();
624 }
625 #endif
626 return Serializer::enabled();
627 } else if (rmode == RelocInfo::NONE) {
628 return false;
629 }
630 return true;
631 }
632
633
634 void Assembler::addrmod1(Instr instr,
635 Register rn,
636 Register rd,
637 const Operand& x) {
638 CheckBuffer();
639 ASSERT((instr & ~(CondMask | OpCodeMask | S)) == 0);
640 if (!x.rm_.is_valid()) {
641 // Immediate.
642 uint32_t rotate_imm;
643 uint32_t immed_8;
644 if (MustUseIp(x.rmode_) ||
645 !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) {
646 // The immediate operand cannot be encoded as a shifter operand, so load
647 // it first to register ip and change the original instruction to use ip.
648 // However, if the original instruction is a 'mov rd, x' (not setting the
649 // condition code), then replace it with a 'ldr rd, [pc]'.
650 RecordRelocInfo(x.rmode_, x.imm32_);
651 CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed
652 Condition cond = static_cast<Condition>(instr & CondMask);
653 if ((instr & ~CondMask) == 13*B21) { // mov, S not set
654 ldr(rd, MemOperand(pc, 0), cond);
655 } else {
656 ldr(ip, MemOperand(pc, 0), cond);
657 addrmod1(instr, rn, rd, Operand(ip));
658 }
659 return;
660 }
661 instr |= I | rotate_imm*B8 | immed_8;
662 } else if (!x.rs_.is_valid()) {
663 // Immediate shift.
664 instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
665 } else {
666 // Register shift.
667 ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
668 instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code();
669 }
670 emit(instr | rn.code()*B16 | rd.code()*B12);
671 if (rn.is(pc) || x.rm_.is(pc))
672 // Block constant pool emission for one instruction after reading pc.
673 BlockConstPoolBefore(pc_offset() + kInstrSize);
674 }
675
676
677 void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
678 ASSERT((instr & ~(CondMask | B | L)) == B26);
679 int am = x.am_;
680 if (!x.rm_.is_valid()) {
681 // Immediate offset.
682 int offset_12 = x.offset_;
683 if (offset_12 < 0) {
684 offset_12 = -offset_12;
685 am ^= U;
686 }
687 if (!is_uint12(offset_12)) {
688 // Immediate offset cannot be encoded, load it first to register ip
689 // rn (and rd in a load) should never be ip, or will be trashed.
690 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
691 mov(ip, Operand(x.offset_), LeaveCC,
692 static_cast<Condition>(instr & CondMask));
693 addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_));
694 return;
695 }
696 ASSERT(offset_12 >= 0); // no masking needed
697 instr |= offset_12;
698 } else {
699 // Register offset (shift_imm_ and shift_op_ are 0) or scaled
700 // register offset the constructors make sure than both shift_imm_
701 // and shift_op_ are initialized.
702 ASSERT(!x.rm_.is(pc));
703 instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
704 }
705 ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
706 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
707 }
708
709
710 void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
711 ASSERT((instr & ~(CondMask | L | S6 | H)) == (B4 | B7));
712 ASSERT(x.rn_.is_valid());
713 int am = x.am_;
714 if (!x.rm_.is_valid()) {
715 // Immediate offset.
716 int offset_8 = x.offset_;
717 if (offset_8 < 0) {
718 offset_8 = -offset_8;
719 am ^= U;
720 }
721 if (!is_uint8(offset_8)) {
722 // Immediate offset cannot be encoded, load it first to register ip
723 // rn (and rd in a load) should never be ip, or will be trashed.
724 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
725 mov(ip, Operand(x.offset_), LeaveCC,
726 static_cast<Condition>(instr & CondMask));
727 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
728 return;
729 }
730 ASSERT(offset_8 >= 0); // no masking needed
731 instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf);
732 } else if (x.shift_imm_ != 0) {
733 // Scaled register offset not supported, load index first
734 // rn (and rd in a load) should never be ip, or will be trashed.
735 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
736 mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC,
737 static_cast<Condition>(instr & CondMask));
738 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
739 return;
740 } else {
741 // Register offset.
742 ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback
743 instr |= x.rm_.code();
744 }
745 ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
746 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
747 }
748
749
750 void Assembler::addrmod4(Instr instr, Register rn, RegList rl) {
751 ASSERT((instr & ~(CondMask | P | U | W | L)) == B27);
752 ASSERT(rl != 0);
753 ASSERT(!rn.is(pc));
754 emit(instr | rn.code()*B16 | rl);
755 }
756
757
758 void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {
759 // Unindexed addressing is not encoded by this function.
760 ASSERT_EQ((B27 | B26),
761 (instr & ~(CondMask | CoprocessorMask | P | U | N | W | L)));
762 ASSERT(x.rn_.is_valid() && !x.rm_.is_valid());
763 int am = x.am_;
764 int offset_8 = x.offset_;
765 ASSERT((offset_8 & 3) == 0); // offset must be an aligned word offset
766 offset_8 >>= 2;
767 if (offset_8 < 0) {
768 offset_8 = -offset_8;
769 am ^= U;
770 }
771 ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte
772 ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
773
774 // Post-indexed addressing requires W == 1; different than in addrmod2/3.
775 if ((am & P) == 0)
776 am |= W;
777
778 ASSERT(offset_8 >= 0); // no masking needed
779 emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8);
780 }
781
782
783 int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {
784 int target_pos;
785 if (L->is_bound()) {
786 target_pos = L->pos();
787 } else {
788 if (L->is_linked()) {
789 target_pos = L->pos(); // L's link
790 } else {
791 target_pos = kEndOfChain;
792 }
793 L->link_to(pc_offset());
794 }
795
796 // Block the emission of the constant pool, since the branch instruction must
797 // be emitted at the pc offset recorded by the label.
798 BlockConstPoolBefore(pc_offset() + kInstrSize);
799 return target_pos - (pc_offset() + kPcLoadDelta);
800 }
801
802
803 void Assembler::label_at_put(Label* L, int at_offset) {
804 int target_pos;
805 if (L->is_bound()) {
806 target_pos = L->pos();
807 } else {
808 if (L->is_linked()) {
809 target_pos = L->pos(); // L's link
810 } else {
811 target_pos = kEndOfChain;
812 }
813 L->link_to(at_offset);
814 instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
815 }
816 }
817
818
819 // Branch instructions.
820 void Assembler::b(int branch_offset, Condition cond) {
821 ASSERT((branch_offset & 3) == 0);
822 int imm24 = branch_offset >> 2;
823 ASSERT(is_int24(imm24));
824 emit(cond | B27 | B25 | (imm24 & Imm24Mask));
825
826 if (cond == al)
827 // Dead code is a good location to emit the constant pool.
828 CheckConstPool(false, false);
829 }
830
831
832 void Assembler::bl(int branch_offset, Condition cond) {
833 ASSERT((branch_offset & 3) == 0);
834 int imm24 = branch_offset >> 2;
835 ASSERT(is_int24(imm24));
836 emit(cond | B27 | B25 | B24 | (imm24 & Imm24Mask));
837 }
838
839
840 void Assembler::blx(int branch_offset) { // v5 and above
841 WriteRecordedPositions();
842 ASSERT((branch_offset & 1) == 0);
843 int h = ((branch_offset & 2) >> 1)*B24;
844 int imm24 = branch_offset >> 2;
845 ASSERT(is_int24(imm24));
846 emit(15 << 28 | B27 | B25 | h | (imm24 & Imm24Mask));
847 }
848
849
850 void Assembler::blx(Register target, Condition cond) { // v5 and above
851 WriteRecordedPositions();
852 ASSERT(!target.is(pc));
853 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | 3*B4 | target.code());
854 }
855
856
857 void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t
858 WriteRecordedPositions();
859 ASSERT(!target.is(pc)); // use of pc is actually allowed, but discouraged
860 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | B4 | target.code());
861 }
862
863
864 // Data-processing instructions.
865
866 // UBFX <Rd>,<Rn>,#<lsb>,#<width - 1>
867 // Instruction details available in ARM DDI 0406A, A8-464.
868 // cond(31-28) | 01111(27-23)| 1(22) | 1(21) | widthm1(20-16) |
869 // Rd(15-12) | lsb(11-7) | 101(6-4) | Rn(3-0)
870 void Assembler::ubfx(Register dst, Register src1, const Operand& src2,
871 const Operand& src3, Condition cond) {
872 ASSERT(!src2.rm_.is_valid() && !src3.rm_.is_valid());
873 ASSERT(static_cast<uint32_t>(src2.imm32_) <= 0x1f);
874 ASSERT(static_cast<uint32_t>(src3.imm32_) <= 0x1f);
875 emit(cond | 0x3F*B21 | src3.imm32_*B16 |
876 dst.code()*B12 | src2.imm32_*B7 | 0x5*B4 | src1.code());
877 }
878
879
880 void Assembler::and_(Register dst, Register src1, const Operand& src2,
881 SBit s, Condition cond) {
882 addrmod1(cond | 0*B21 | s, src1, dst, src2);
883 }
884
885
886 void Assembler::eor(Register dst, Register src1, const Operand& src2,
887 SBit s, Condition cond) {
888 addrmod1(cond | 1*B21 | s, src1, dst, src2);
889 }
890
891
892 void Assembler::sub(Register dst, Register src1, const Operand& src2,
893 SBit s, Condition cond) {
894 addrmod1(cond | 2*B21 | s, src1, dst, src2);
895 }
896
897
898 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
899 SBit s, Condition cond) {
900 addrmod1(cond | 3*B21 | s, src1, dst, src2);
901 }
902
903
904 void Assembler::add(Register dst, Register src1, const Operand& src2,
905 SBit s, Condition cond) {
906 addrmod1(cond | 4*B21 | s, src1, dst, src2);
907
908 // Eliminate pattern: push(r), pop()
909 // str(src, MemOperand(sp, 4, NegPreIndex), al);
910 // add(sp, sp, Operand(kPointerSize));
911 // Both instructions can be eliminated.
912 int pattern_size = 2 * kInstrSize;
913 if (FLAG_push_pop_elimination &&
914 last_bound_pos_ <= (pc_offset() - pattern_size) &&
915 reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
916 // Pattern.
917 instr_at(pc_ - 1 * kInstrSize) == kPopInstruction &&
918 (instr_at(pc_ - 2 * kInstrSize) & ~RdMask) == kPushRegPattern) {
919 pc_ -= 2 * kInstrSize;
920 if (FLAG_print_push_pop_elimination) {
921 PrintF("%x push(reg)/pop() eliminated\n", pc_offset());
922 }
923 }
924 }
925
926
927 void Assembler::adc(Register dst, Register src1, const Operand& src2,
928 SBit s, Condition cond) {
929 addrmod1(cond | 5*B21 | s, src1, dst, src2);
930 }
931
932
933 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
934 SBit s, Condition cond) {
935 addrmod1(cond | 6*B21 | s, src1, dst, src2);
936 }
937
938
939 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
940 SBit s, Condition cond) {
941 addrmod1(cond | 7*B21 | s, src1, dst, src2);
942 }
943
944
945 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
946 addrmod1(cond | 8*B21 | S, src1, r0, src2);
947 }
948
949
950 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
951 addrmod1(cond | 9*B21 | S, src1, r0, src2);
952 }
953
954
955 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
956 addrmod1(cond | 10*B21 | S, src1, r0, src2);
957 }
958
959
960 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
961 addrmod1(cond | 11*B21 | S, src1, r0, src2);
962 }
963
964
965 void Assembler::orr(Register dst, Register src1, const Operand& src2,
966 SBit s, Condition cond) {
967 addrmod1(cond | 12*B21 | s, src1, dst, src2);
968 }
969
970
971 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
972 if (dst.is(pc)) {
973 WriteRecordedPositions();
974 }
975 addrmod1(cond | 13*B21 | s, r0, dst, src);
976 }
977
978
979 void Assembler::bic(Register dst, Register src1, const Operand& src2,
980 SBit s, Condition cond) {
981 addrmod1(cond | 14*B21 | s, src1, dst, src2);
982 }
983
984
985 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
986 addrmod1(cond | 15*B21 | s, r0, dst, src);
987 }
988
989
990 // Multiply instructions.
991 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
992 SBit s, Condition cond) {
993 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
994 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 |
995 src2.code()*B8 | B7 | B4 | src1.code());
996 }
997
998
999 void Assembler::mul(Register dst, Register src1, Register src2,
1000 SBit s, Condition cond) {
1001 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1002 // dst goes in bits 16-19 for this instruction!
1003 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
1004 }
1005
1006
1007 void Assembler::smlal(Register dstL,
1008 Register dstH,
1009 Register src1,
1010 Register src2,
1011 SBit s,
1012 Condition cond) {
1013 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1014 ASSERT(!dstL.is(dstH));
1015 emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 |
1016 src2.code()*B8 | B7 | B4 | src1.code());
1017 }
1018
1019
1020 void Assembler::smull(Register dstL,
1021 Register dstH,
1022 Register src1,
1023 Register src2,
1024 SBit s,
1025 Condition cond) {
1026 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1027 ASSERT(!dstL.is(dstH));
1028 emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 |
1029 src2.code()*B8 | B7 | B4 | src1.code());
1030 }
1031
1032
1033 void Assembler::umlal(Register dstL,
1034 Register dstH,
1035 Register src1,
1036 Register src2,
1037 SBit s,
1038 Condition cond) {
1039 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1040 ASSERT(!dstL.is(dstH));
1041 emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 |
1042 src2.code()*B8 | B7 | B4 | src1.code());
1043 }
1044
1045
1046 void Assembler::umull(Register dstL,
1047 Register dstH,
1048 Register src1,
1049 Register src2,
1050 SBit s,
1051 Condition cond) {
1052 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1053 ASSERT(!dstL.is(dstH));
1054 emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 |
1055 src2.code()*B8 | B7 | B4 | src1.code());
1056 }
1057
1058
1059 // Miscellaneous arithmetic instructions.
1060 void Assembler::clz(Register dst, Register src, Condition cond) {
1061 // v5 and above.
1062 ASSERT(!dst.is(pc) && !src.is(pc));
1063 emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 |
1064 15*B8 | B4 | src.code());
1065 }
1066
1067
1068 // Status register access instructions.
1069 void Assembler::mrs(Register dst, SRegister s, Condition cond) {
1070 ASSERT(!dst.is(pc));
1071 emit(cond | B24 | s | 15*B16 | dst.code()*B12);
1072 }
1073
1074
1075 void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
1076 Condition cond) {
1077 ASSERT(fields >= B16 && fields < B20); // at least one field set
1078 Instr instr;
1079 if (!src.rm_.is_valid()) {
1080 // Immediate.
1081 uint32_t rotate_imm;
1082 uint32_t immed_8;
1083 if (MustUseIp(src.rmode_) ||
1084 !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) {
1085 // Immediate operand cannot be encoded, load it first to register ip.
1086 RecordRelocInfo(src.rmode_, src.imm32_);
1087 ldr(ip, MemOperand(pc, 0), cond);
1088 msr(fields, Operand(ip), cond);
1089 return;
1090 }
1091 instr = I | rotate_imm*B8 | immed_8;
1092 } else {
1093 ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0); // only rm allowed
1094 instr = src.rm_.code();
1095 }
1096 emit(cond | instr | B24 | B21 | fields | 15*B12);
1097 }
1098
1099
1100 // Load/Store instructions.
1101 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
1102 if (dst.is(pc)) {
1103 WriteRecordedPositions();
1104 }
1105 addrmod2(cond | B26 | L, dst, src);
1106
1107 // Eliminate pattern: push(r), pop(r)
1108 // str(r, MemOperand(sp, 4, NegPreIndex), al)
1109 // ldr(r, MemOperand(sp, 4, PostIndex), al)
1110 // Both instructions can be eliminated.
1111 int pattern_size = 2 * kInstrSize;
1112 if (FLAG_push_pop_elimination &&
1113 last_bound_pos_ <= (pc_offset() - pattern_size) &&
1114 reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
1115 // Pattern.
1116 instr_at(pc_ - 1 * kInstrSize) == (kPopRegPattern | dst.code() * B12) &&
1117 instr_at(pc_ - 2 * kInstrSize) == (kPushRegPattern | dst.code() * B12)) {
1118 pc_ -= 2 * kInstrSize;
1119 if (FLAG_print_push_pop_elimination) {
1120 PrintF("%x push/pop (same reg) eliminated\n", pc_offset());
1121 }
1122 }
1123 }
1124
1125
1126 void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
1127 addrmod2(cond | B26, src, dst);
1128
1129 // Eliminate pattern: pop(), push(r)
1130 // add sp, sp, #4 LeaveCC, al; str r, [sp, #-4], al
1131 // -> str r, [sp, 0], al
1132 int pattern_size = 2 * kInstrSize;
1133 if (FLAG_push_pop_elimination &&
1134 last_bound_pos_ <= (pc_offset() - pattern_size) &&
1135 reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
1136 // Pattern.
1137 instr_at(pc_ - 1 * kInstrSize) == (kPushRegPattern | src.code() * B12) &&
1138 instr_at(pc_ - 2 * kInstrSize) == kPopInstruction) {
1139 pc_ -= 2 * kInstrSize;
1140 emit(al | B26 | 0 | Offset | sp.code() * B16 | src.code() * B12);
1141 if (FLAG_print_push_pop_elimination) {
1142 PrintF("%x pop()/push(reg) eliminated\n", pc_offset());
1143 }
1144 }
1145 }
1146
1147
1148 void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
1149 addrmod2(cond | B26 | B | L, dst, src);
1150 }
1151
1152
1153 void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
1154 addrmod2(cond | B26 | B, src, dst);
1155 }
1156
1157
1158 void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
1159 addrmod3(cond | L | B7 | H | B4, dst, src);
1160 }
1161
1162
1163 void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
1164 addrmod3(cond | B7 | H | B4, src, dst);
1165 }
1166
1167
1168 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
1169 addrmod3(cond | L | B7 | S6 | B4, dst, src);
1170 }
1171
1172
1173 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
1174 addrmod3(cond | L | B7 | S6 | H | B4, dst, src);
1175 }
1176
1177
1178 // Load/Store multiple instructions.
1179 void Assembler::ldm(BlockAddrMode am,
1180 Register base,
1181 RegList dst,
1182 Condition cond) {
1183 // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable.
1184 ASSERT(base.is(sp) || (dst & sp.bit()) == 0);
1185
1186 addrmod4(cond | B27 | am | L, base, dst);
1187
1188 // Emit the constant pool after a function return implemented by ldm ..{..pc}.
1189 if (cond == al && (dst & pc.bit()) != 0) {
1190 // There is a slight chance that the ldm instruction was actually a call,
1191 // in which case it would be wrong to return into the constant pool; we
1192 // recognize this case by checking if the emission of the pool was blocked
1193 // at the pc of the ldm instruction by a mov lr, pc instruction; if this is
1194 // the case, we emit a jump over the pool.
1195 CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize);
1196 }
1197 }
1198
1199
1200 void Assembler::stm(BlockAddrMode am,
1201 Register base,
1202 RegList src,
1203 Condition cond) {
1204 addrmod4(cond | B27 | am, base, src);
1205 }
1206
1207
1208 // Exception-generating instructions and debugging support.
1209 void Assembler::stop(const char* msg) {
1210 #if !defined(__arm__)
1211 // The simulator handles these special instructions and stops execution.
1212 emit(15 << 28 | ((intptr_t) msg));
1213 #else
1214 // Just issue a simple break instruction for now. Alternatively we could use
1215 // the swi(0x9f0001) instruction on Linux.
1216 bkpt(0);
1217 #endif
1218 }
1219
1220
1221 void Assembler::bkpt(uint32_t imm16) { // v5 and above
1222 ASSERT(is_uint16(imm16));
1223 emit(al | B24 | B21 | (imm16 >> 4)*B8 | 7*B4 | (imm16 & 0xf));
1224 }
1225
1226
1227 void Assembler::swi(uint32_t imm24, Condition cond) {
1228 ASSERT(is_uint24(imm24));
1229 emit(cond | 15*B24 | imm24);
1230 }
1231
1232
1233 // Coprocessor instructions.
1234 void Assembler::cdp(Coprocessor coproc,
1235 int opcode_1,
1236 CRegister crd,
1237 CRegister crn,
1238 CRegister crm,
1239 int opcode_2,
1240 Condition cond) {
1241 ASSERT(is_uint4(opcode_1) && is_uint3(opcode_2));
1242 emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 |
1243 crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code());
1244 }
1245
1246
1247 void Assembler::cdp2(Coprocessor coproc,
1248 int opcode_1,
1249 CRegister crd,
1250 CRegister crn,
1251 CRegister crm,
1252 int opcode_2) { // v5 and above
1253 cdp(coproc, opcode_1, crd, crn, crm, opcode_2, static_cast<Condition>(nv));
1254 }
1255
1256
1257 void Assembler::mcr(Coprocessor coproc,
1258 int opcode_1,
1259 Register rd,
1260 CRegister crn,
1261 CRegister crm,
1262 int opcode_2,
1263 Condition cond) {
1264 ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2));
1265 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 |
1266 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
1267 }
1268
1269
1270 void Assembler::mcr2(Coprocessor coproc,
1271 int opcode_1,
1272 Register rd,
1273 CRegister crn,
1274 CRegister crm,
1275 int opcode_2) { // v5 and above
1276 mcr(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv));
1277 }
1278
1279
1280 void Assembler::mrc(Coprocessor coproc,
1281 int opcode_1,
1282 Register rd,
1283 CRegister crn,
1284 CRegister crm,
1285 int opcode_2,
1286 Condition cond) {
1287 ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2));
1288 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 |
1289 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
1290 }
1291
1292
1293 void Assembler::mrc2(Coprocessor coproc,
1294 int opcode_1,
1295 Register rd,
1296 CRegister crn,
1297 CRegister crm,
1298 int opcode_2) { // v5 and above
1299 mrc(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv));
1300 }
1301
1302
1303 void Assembler::ldc(Coprocessor coproc,
1304 CRegister crd,
1305 const MemOperand& src,
1306 LFlag l,
1307 Condition cond) {
1308 addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src);
1309 }
1310
1311
1312 void Assembler::ldc(Coprocessor coproc,
1313 CRegister crd,
1314 Register rn,
1315 int option,
1316 LFlag l,
1317 Condition cond) {
1318 // Unindexed addressing.
1319 ASSERT(is_uint8(option));
1320 emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 |
1321 coproc*B8 | (option & 255));
1322 }
1323
1324
1325 void Assembler::ldc2(Coprocessor coproc,
1326 CRegister crd,
1327 const MemOperand& src,
1328 LFlag l) { // v5 and above
1329 ldc(coproc, crd, src, l, static_cast<Condition>(nv));
1330 }
1331
1332
1333 void Assembler::ldc2(Coprocessor coproc,
1334 CRegister crd,
1335 Register rn,
1336 int option,
1337 LFlag l) { // v5 and above
1338 ldc(coproc, crd, rn, option, l, static_cast<Condition>(nv));
1339 }
1340
1341
1342 void Assembler::stc(Coprocessor coproc,
1343 CRegister crd,
1344 const MemOperand& dst,
1345 LFlag l,
1346 Condition cond) {
1347 addrmod5(cond | B27 | B26 | l | coproc*B8, crd, dst);
1348 }
1349
1350
1351 void Assembler::stc(Coprocessor coproc,
1352 CRegister crd,
1353 Register rn,
1354 int option,
1355 LFlag l,
1356 Condition cond) {
1357 // Unindexed addressing.
1358 ASSERT(is_uint8(option));
1359 emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 |
1360 coproc*B8 | (option & 255));
1361 }
1362
1363
1364 void Assembler::stc2(Coprocessor
1365 coproc, CRegister crd,
1366 const MemOperand& dst,
1367 LFlag l) { // v5 and above
1368 stc(coproc, crd, dst, l, static_cast<Condition>(nv));
1369 }
1370
1371
1372 void Assembler::stc2(Coprocessor coproc,
1373 CRegister crd,
1374 Register rn,
1375 int option,
1376 LFlag l) { // v5 and above
1377 stc(coproc, crd, rn, option, l, static_cast<Condition>(nv));
1378 }
1379
1380
1381 // Support for VFP.
1382 void Assembler::vldr(const DwVfpRegister dst,
1383 const Register base,
1384 int offset,
1385 const Condition cond) {
1386 // Ddst = MEM(Rbase + offset).
1387 // Instruction details available in ARM DDI 0406A, A8-628.
1388 // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) |
1389 // Vdst(15-12) | 1011(11-8) | offset
1390 ASSERT(CpuFeatures::IsEnabled(VFP3));
1391 ASSERT(offset % 4 == 0);
1392 emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 |
1393 0xB*B8 | ((offset / 4) & 255));
1394 }
1395
1396
1397 void Assembler::vstr(const DwVfpRegister src,
1398 const Register base,
1399 int offset,
1400 const Condition cond) {
1401 // MEM(Rbase + offset) = Dsrc.
1402 // Instruction details available in ARM DDI 0406A, A8-786.
1403 // cond(31-28) | 1101(27-24)| 1000(23-20) | | Rbase(19-16) |
1404 // Vsrc(15-12) | 1011(11-8) | (offset/4)
1405 ASSERT(CpuFeatures::IsEnabled(VFP3));
1406 ASSERT(offset % 4 == 0);
1407 emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 |
1408 0xB*B8 | ((offset / 4) & 255));
1409 }
1410
1411
1412 void Assembler::vmov(const DwVfpRegister dst,
1413 const Register src1,
1414 const Register src2,
1415 const Condition cond) {
1416 // Dm = <Rt,Rt2>.
1417 // Instruction details available in ARM DDI 0406A, A8-646.
1418 // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) |
1419 // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
1420 ASSERT(CpuFeatures::IsEnabled(VFP3));
1421 ASSERT(!src1.is(pc) && !src2.is(pc));
1422 emit(cond | 0xC*B24 | B22 | src2.code()*B16 |
1423 src1.code()*B12 | 0xB*B8 | B4 | dst.code());
1424 }
1425
1426
1427 void Assembler::vmov(const Register dst1,
1428 const Register dst2,
1429 const DwVfpRegister src,
1430 const Condition cond) {
1431 // <Rt,Rt2> = Dm.
1432 // Instruction details available in ARM DDI 0406A, A8-646.
1433 // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) |
1434 // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
1435 ASSERT(CpuFeatures::IsEnabled(VFP3));
1436 ASSERT(!dst1.is(pc) && !dst2.is(pc));
1437 emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 |
1438 dst1.code()*B12 | 0xB*B8 | B4 | src.code());
1439 }
1440
1441
1442 void Assembler::vmov(const SwVfpRegister dst,
1443 const Register src,
1444 const Condition cond) {
1445 // Sn = Rt.
1446 // Instruction details available in ARM DDI 0406A, A8-642.
1447 // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) |
1448 // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
1449 ASSERT(CpuFeatures::IsEnabled(VFP3));
1450 ASSERT(!src.is(pc));
1451 emit(cond | 0xE*B24 | (dst.code() >> 1)*B16 |
1452 src.code()*B12 | 0xA*B8 | (0x1 & dst.code())*B7 | B4);
1453 }
1454
1455
1456 void Assembler::vmov(const Register dst,
1457 const SwVfpRegister src,
1458 const Condition cond) {
1459 // Rt = Sn.
1460 // Instruction details available in ARM DDI 0406A, A8-642.
1461 // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) |
1462 // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
1463 ASSERT(CpuFeatures::IsEnabled(VFP3));
1464 ASSERT(!dst.is(pc));
1465 emit(cond | 0xE*B24 | B20 | (src.code() >> 1)*B16 |
1466 dst.code()*B12 | 0xA*B8 | (0x1 & src.code())*B7 | B4);
1467 }
1468
1469
1470 void Assembler::vcvt(const DwVfpRegister dst,
1471 const SwVfpRegister src,
1472 const Condition cond) {
1473 // Dd = Sm (integer in Sm converted to IEEE 64-bit doubles in Dd).
1474 // Instruction details available in ARM DDI 0406A, A8-576.
1475 // cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) | opc2=000(18-16) |
1476 // Vd(15-12) | 101(11-9) | sz(8)=1 | op(7)=1 | 1(6) | M=?(5) | 0(4) | Vm(3-0)
1477 ASSERT(CpuFeatures::IsEnabled(VFP3));
1478 emit(cond | 0xE*B24 | B23 | 0x3*B20 | B19 |
1479 dst.code()*B12 | 0x5*B9 | B8 | B7 | B6 |
1480 (0x1 & src.code())*B5 | (src.code() >> 1));
1481 }
1482
1483
1484 void Assembler::vcvt(const SwVfpRegister dst,
1485 const DwVfpRegister src,
1486 const Condition cond) {
1487 // Sd = Dm (IEEE 64-bit doubles in Dm converted to 32 bit integer in Sd).
1488 // Instruction details available in ARM DDI 0406A, A8-576.
1489 // cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) | opc2=101(18-16)|
1490 // Vd(15-12) | 101(11-9) | sz(8)=1 | op(7)=? | 1(6) | M=?(5) | 0(4) | Vm(3-0)
1491 ASSERT(CpuFeatures::IsEnabled(VFP3));
1492 emit(cond | 0xE*B24 | B23 |(0x1 & dst.code())*B22 |
1493 0x3*B20 | B19 | 0x5*B16 | (dst.code() >> 1)*B12 |
1494 0x5*B9 | B8 | B7 | B6 | src.code());
1495 }
1496
1497
1498 void Assembler::vadd(const DwVfpRegister dst,
1499 const DwVfpRegister src1,
1500 const DwVfpRegister src2,
1501 const Condition cond) {
1502 // Dd = vadd(Dn, Dm) double precision floating point addition.
1503 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1504 // Instruction details available in ARM DDI 0406A, A8-536.
1505 // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
1506 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
1507 ASSERT(CpuFeatures::IsEnabled(VFP3));
1508 emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1509 dst.code()*B12 | 0x5*B9 | B8 | src2.code());
1510 }
1511
1512
1513 void Assembler::vsub(const DwVfpRegister dst,
1514 const DwVfpRegister src1,
1515 const DwVfpRegister src2,
1516 const Condition cond) {
1517 // Dd = vsub(Dn, Dm) double precision floating point subtraction.
1518 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1519 // Instruction details available in ARM DDI 0406A, A8-784.
1520 // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
1521 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 1(6) | M=?(5) | 0(4) | Vm(3-0)
1522 ASSERT(CpuFeatures::IsEnabled(VFP3));
1523 emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1524 dst.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
1525 }
1526
1527
1528 void Assembler::vmul(const DwVfpRegister dst,
1529 const DwVfpRegister src1,
1530 const DwVfpRegister src2,
1531 const Condition cond) {
1532 // Dd = vmul(Dn, Dm) double precision floating point multiplication.
1533 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1534 // Instruction details available in ARM DDI 0406A, A8-784.
1535 // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) |
1536 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
1537 ASSERT(CpuFeatures::IsEnabled(VFP3));
1538 emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 |
1539 dst.code()*B12 | 0x5*B9 | B8 | src2.code());
1540 }
1541
1542
1543 void Assembler::vdiv(const DwVfpRegister dst,
1544 const DwVfpRegister src1,
1545 const DwVfpRegister src2,
1546 const Condition cond) {
1547 // Dd = vdiv(Dn, Dm) double precision floating point division.
1548 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
1549 // Instruction details available in ARM DDI 0406A, A8-584.
1550 // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) |
1551 // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0)
1552 ASSERT(CpuFeatures::IsEnabled(VFP3));
1553 emit(cond | 0xE*B24 | B23 | src1.code()*B16 |
1554 dst.code()*B12 | 0x5*B9 | B8 | src2.code());
1555 }
1556
1557
1558 void Assembler::vcmp(const DwVfpRegister src1,
1559 const DwVfpRegister src2,
1560 const SBit s,
1561 const Condition cond) {
1562 // vcmp(Dd, Dm) double precision floating point comparison.
1563 // Instruction details available in ARM DDI 0406A, A8-570.
1564 // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) |
1565 // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | Vm(3-0)
1566 ASSERT(CpuFeatures::IsEnabled(VFP3));
1567 emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 |
1568 src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
1569 }
1570
1571
1572 void Assembler::vmrs(Register dst, Condition cond) {
1573 // Instruction details available in ARM DDI 0406A, A8-652.
1574 // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) |
1575 // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0)
1576 ASSERT(CpuFeatures::IsEnabled(VFP3));
1577 emit(cond | 0xE*B24 | 0xF*B20 | B16 |
1578 dst.code()*B12 | 0xA*B8 | B4);
1579 }
1580
1581
1582 bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
1583 uint32_t dummy1;
1584 uint32_t dummy2;
1585 return fits_shifter(imm32, &dummy1, &dummy2, NULL);
1586 }
1587
1588
1589 void Assembler::BlockConstPoolFor(int instructions) {
1590 BlockConstPoolBefore(pc_offset() + instructions * kInstrSize);
1591 }
1592
1593
1594 // Debugging.
1595 void Assembler::RecordJSReturn() {
1596 WriteRecordedPositions();
1597 CheckBuffer();
1598 RecordRelocInfo(RelocInfo::JS_RETURN);
1599 }
1600
1601
1602 void Assembler::RecordComment(const char* msg) {
1603 if (FLAG_debug_code) {
1604 CheckBuffer();
1605 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
1606 }
1607 }
1608
1609
1610 void Assembler::RecordPosition(int pos) {
1611 if (pos == RelocInfo::kNoPosition) return;
1612 ASSERT(pos >= 0);
1613 current_position_ = pos;
1614 }
1615
1616
1617 void Assembler::RecordStatementPosition(int pos) {
1618 if (pos == RelocInfo::kNoPosition) return;
1619 ASSERT(pos >= 0);
1620 current_statement_position_ = pos;
1621 }
1622
1623
1624 void Assembler::WriteRecordedPositions() {
1625 // Write the statement position if it is different from what was written last
1626 // time.
1627 if (current_statement_position_ != written_statement_position_) {
1628 CheckBuffer();
1629 RecordRelocInfo(RelocInfo::STATEMENT_POSITION, current_statement_position_);
1630 written_statement_position_ = current_statement_position_;
1631 }
1632
1633 // Write the position if it is different from what was written last time and
1634 // also different from the written statement position.
1635 if (current_position_ != written_position_ &&
1636 current_position_ != written_statement_position_) {
1637 CheckBuffer();
1638 RecordRelocInfo(RelocInfo::POSITION, current_position_);
1639 written_position_ = current_position_;
1640 }
1641 }
1642
1643
1644 void Assembler::GrowBuffer() {
1645 if (!own_buffer_) FATAL("external code buffer is too small");
1646
1647 // Compute new buffer size.
1648 CodeDesc desc; // the new buffer
1649 if (buffer_size_ < 4*KB) {
1650 desc.buffer_size = 4*KB;
1651 } else if (buffer_size_ < 1*MB) {
1652 desc.buffer_size = 2*buffer_size_;
1653 } else {
1654 desc.buffer_size = buffer_size_ + 1*MB;
1655 }
1656 CHECK_GT(desc.buffer_size, 0); // no overflow
1657
1658 // Setup new buffer.
1659 desc.buffer = NewArray<byte>(desc.buffer_size);
1660
1661 desc.instr_size = pc_offset();
1662 desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
1663
1664 // Copy the data.
1665 int pc_delta = desc.buffer - buffer_;
1666 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
1667 memmove(desc.buffer, buffer_, desc.instr_size);
1668 memmove(reloc_info_writer.pos() + rc_delta,
1669 reloc_info_writer.pos(), desc.reloc_size);
1670
1671 // Switch buffers.
1672 DeleteArray(buffer_);
1673 buffer_ = desc.buffer;
1674 buffer_size_ = desc.buffer_size;
1675 pc_ += pc_delta;
1676 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
1677 reloc_info_writer.last_pc() + pc_delta);
1678
1679 // None of our relocation types are pc relative pointing outside the code
1680 // buffer nor pc absolute pointing inside the code buffer, so there is no need
1681 // to relocate any emitted relocation entries.
1682
1683 // Relocate pending relocation entries.
1684 for (int i = 0; i < num_prinfo_; i++) {
1685 RelocInfo& rinfo = prinfo_[i];
1686 ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
1687 rinfo.rmode() != RelocInfo::POSITION);
1688 if (rinfo.rmode() != RelocInfo::JS_RETURN) {
1689 rinfo.set_pc(rinfo.pc() + pc_delta);
1690 }
1691 }
1692 }
1693
1694
1695 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
1696 RelocInfo rinfo(pc_, rmode, data); // we do not try to reuse pool constants
1697 if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::STATEMENT_POSITION) {
1698 // Adjust code for new modes.
1699 ASSERT(RelocInfo::IsJSReturn(rmode)
1700 || RelocInfo::IsComment(rmode)
1701 || RelocInfo::IsPosition(rmode));
1702 // These modes do not need an entry in the constant pool.
1703 } else {
1704 ASSERT(num_prinfo_ < kMaxNumPRInfo);
1705 prinfo_[num_prinfo_++] = rinfo;
1706 // Make sure the constant pool is not emitted in place of the next
1707 // instruction for which we just recorded relocation info.
1708 BlockConstPoolBefore(pc_offset() + kInstrSize);
1709 }
1710 if (rinfo.rmode() != RelocInfo::NONE) {
1711 // Don't record external references unless the heap will be serialized.
1712 if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
1713 #ifdef DEBUG
1714 if (!Serializer::enabled()) {
1715 Serializer::TooLateToEnableNow();
1716 }
1717 #endif
1718 if (!Serializer::enabled() && !FLAG_debug_code) {
1719 return;
1720 }
1721 }
1722 ASSERT(buffer_space() >= kMaxRelocSize); // too late to grow buffer here
1723 reloc_info_writer.Write(&rinfo);
1724 }
1725 }
1726
1727
1728 void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
1729 // Calculate the offset of the next check. It will be overwritten
1730 // when a const pool is generated or when const pools are being
1731 // blocked for a specific range.
1732 next_buffer_check_ = pc_offset() + kCheckConstInterval;
1733
1734 // There is nothing to do if there are no pending relocation info entries.
1735 if (num_prinfo_ == 0) return;
1736
1737 // We emit a constant pool at regular intervals of about kDistBetweenPools
1738 // or when requested by parameter force_emit (e.g. after each function).
1739 // We prefer not to emit a jump unless the max distance is reached or if we
1740 // are running low on slots, which can happen if a lot of constants are being
1741 // emitted (e.g. --debug-code and many static references).
1742 int dist = pc_offset() - last_const_pool_end_;
1743 if (!force_emit && dist < kMaxDistBetweenPools &&
1744 (require_jump || dist < kDistBetweenPools) &&
1745 // TODO(1236125): Cleanup the "magic" number below. We know that
1746 // the code generation will test every kCheckConstIntervalInst.
1747 // Thus we are safe as long as we generate less than 7 constant
1748 // entries per instruction.
1749 (num_prinfo_ < (kMaxNumPRInfo - (7 * kCheckConstIntervalInst)))) {
1750 return;
1751 }
1752
1753 // If we did not return by now, we need to emit the constant pool soon.
1754
1755 // However, some small sequences of instructions must not be broken up by the
1756 // insertion of a constant pool; such sequences are protected by setting
1757 // no_const_pool_before_, which is checked here. Also, recursive calls to
1758 // CheckConstPool are blocked by no_const_pool_before_.
1759 if (pc_offset() < no_const_pool_before_) {
1760 // Emission is currently blocked; make sure we try again as soon as
1761 // possible.
1762 next_buffer_check_ = no_const_pool_before_;
1763
1764 // Something is wrong if emission is forced and blocked at the same time.
1765 ASSERT(!force_emit);
1766 return;
1767 }
1768
1769 int jump_instr = require_jump ? kInstrSize : 0;
1770
1771 // Check that the code buffer is large enough before emitting the constant
1772 // pool and relocation information (include the jump over the pool and the
1773 // constant pool marker).
1774 int max_needed_space =
1775 jump_instr + kInstrSize + num_prinfo_*(kInstrSize + kMaxRelocSize);
1776 while (buffer_space() <= (max_needed_space + kGap)) GrowBuffer();
1777
1778 // Block recursive calls to CheckConstPool.
1779 BlockConstPoolBefore(pc_offset() + jump_instr + kInstrSize +
1780 num_prinfo_*kInstrSize);
1781 // Don't bother to check for the emit calls below.
1782 next_buffer_check_ = no_const_pool_before_;
1783
1784 // Emit jump over constant pool if necessary.
1785 Label after_pool;
1786 if (require_jump) b(&after_pool);
1787
1788 RecordComment("[ Constant Pool");
1789
1790 // Put down constant pool marker "Undefined instruction" as specified by
1791 // A3.1 Instruction set encoding.
1792 emit(0x03000000 | num_prinfo_);
1793
1794 // Emit constant pool entries.
1795 for (int i = 0; i < num_prinfo_; i++) {
1796 RelocInfo& rinfo = prinfo_[i];
1797 ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
1798 rinfo.rmode() != RelocInfo::POSITION &&
1799 rinfo.rmode() != RelocInfo::STATEMENT_POSITION);
1800 Instr instr = instr_at(rinfo.pc());
1801
1802 // Instruction to patch must be a ldr/str [pc, #offset].
1803 // P and U set, B and W clear, Rn == pc, offset12 still 0.
1804 ASSERT((instr & (7*B25 | P | U | B | W | 15*B16 | Off12Mask)) ==
1805 (2*B25 | P | U | pc.code()*B16));
1806 int delta = pc_ - rinfo.pc() - 8;
1807 ASSERT(delta >= -4); // instr could be ldr pc, [pc, #-4] followed by targ32
1808 if (delta < 0) {
1809 instr &= ~U;
1810 delta = -delta;
1811 }
1812 ASSERT(is_uint12(delta));
1813 instr_at_put(rinfo.pc(), instr + delta);
1814 emit(rinfo.data());
1815 }
1816 num_prinfo_ = 0;
1817 last_const_pool_end_ = pc_offset();
1818
1819 RecordComment("]");
1820
1821 if (after_pool.is_linked()) {
1822 bind(&after_pool);
1823 }
1824
1825 // Since a constant pool was just emitted, move the check offset forward by
1826 // the standard interval.
1827 next_buffer_check_ = pc_offset() + kCheckConstInterval;
1828 }
1829
1830
1831 } } // namespace v8::internal
1832
1833 #endif // V8_TARGET_ARCH_ARM && V8_ARM_VARIANT_THUMB
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