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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 73 bool is(Register reg) const { return code_ == reg.code_; } | 73 bool is(Register reg) const { return code_ == reg.code_; } |
| 74 int code() const { | 74 int code() const { |
| 75 ASSERT(is_valid()); | 75 ASSERT(is_valid()); |
| 76 return code_; | 76 return code_; |
| 77 } | 77 } |
| 78 int bit() const { | 78 int bit() const { |
| 79 ASSERT(is_valid()); | 79 ASSERT(is_valid()); |
| 80 return 1 << code_; | 80 return 1 << code_; |
| 81 } | 81 } |
| 82 | 82 |
| 83 void set_code(int code) { |
| 84 code_ = code; |
| 85 ASSERT(is_valid()); |
| 86 } |
| 87 |
| 83 // Unfortunately we can't make this private in a struct. | 88 // Unfortunately we can't make this private in a struct. |
| 84 int code_; | 89 int code_; |
| 85 }; | 90 }; |
| 86 | 91 |
| 87 const Register no_reg = { -1 }; | 92 const Register no_reg = { -1 }; |
| 88 | 93 |
| 89 const Register r0 = { 0 }; | 94 const Register r0 = { 0 }; |
| 90 const Register r1 = { 1 }; | 95 const Register r1 = { 1 }; |
| 91 const Register r2 = { 2 }; | 96 const Register r2 = { 2 }; |
| 92 const Register r3 = { 3 }; | 97 const Register r3 = { 3 }; |
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| 451 void set_offset(int32_t offset) { | 456 void set_offset(int32_t offset) { |
| 452 ASSERT(rm_.is(no_reg)); | 457 ASSERT(rm_.is(no_reg)); |
| 453 offset_ = offset; | 458 offset_ = offset; |
| 454 } | 459 } |
| 455 | 460 |
| 456 uint32_t offset() { | 461 uint32_t offset() { |
| 457 ASSERT(rm_.is(no_reg)); | 462 ASSERT(rm_.is(no_reg)); |
| 458 return offset_; | 463 return offset_; |
| 459 } | 464 } |
| 460 | 465 |
| 461 Register rm() const {return rm_;} | 466 Register rn() const { return rn_; } |
| 467 Register rm() const { return rm_; } |
| 462 | 468 |
| 463 private: | 469 private: |
| 464 Register rn_; // base | 470 Register rn_; // base |
| 465 Register rm_; // register offset | 471 Register rm_; // register offset |
| 466 int32_t offset_; // valid if rm_ == no_reg | 472 int32_t offset_; // valid if rm_ == no_reg |
| 467 ShiftOp shift_op_; | 473 ShiftOp shift_op_; |
| 468 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg | 474 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg |
| 469 AddrMode am_; // bits P, U, and W | 475 AddrMode am_; // bits P, U, and W |
| 470 | 476 |
| 471 friend class Assembler; | 477 friend class Assembler; |
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| 1134 | 1140 |
| 1135 friend class RegExpMacroAssemblerARM; | 1141 friend class RegExpMacroAssemblerARM; |
| 1136 friend class RelocInfo; | 1142 friend class RelocInfo; |
| 1137 friend class CodePatcher; | 1143 friend class CodePatcher; |
| 1138 friend class BlockConstPoolScope; | 1144 friend class BlockConstPoolScope; |
| 1139 }; | 1145 }; |
| 1140 | 1146 |
| 1141 } } // namespace v8::internal | 1147 } } // namespace v8::internal |
| 1142 | 1148 |
| 1143 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1149 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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