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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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101 #endif | 101 #endif |
102 } | 102 } |
103 | 103 |
104 | 104 |
105 // ----------------------------------------------------------------------------- | 105 // ----------------------------------------------------------------------------- |
106 // Implementation of RelocInfo | 106 // Implementation of RelocInfo |
107 | 107 |
108 const int RelocInfo::kApplyMask = 0; | 108 const int RelocInfo::kApplyMask = 0; |
109 | 109 |
110 | 110 |
| 111 bool RelocInfo::IsCodedSpecially() { |
| 112 // The deserializer needs to know whether a pointer is specially coded. Being |
| 113 // specially coded on ARM means that it is a movw/movt instruction. We don't |
| 114 // generate those yet. |
| 115 return false; |
| 116 } |
| 117 |
| 118 |
| 119 |
111 void RelocInfo::PatchCode(byte* instructions, int instruction_count) { | 120 void RelocInfo::PatchCode(byte* instructions, int instruction_count) { |
112 // Patch the code at the current address with the supplied instructions. | 121 // Patch the code at the current address with the supplied instructions. |
113 Instr* pc = reinterpret_cast<Instr*>(pc_); | 122 Instr* pc = reinterpret_cast<Instr*>(pc_); |
114 Instr* instr = reinterpret_cast<Instr*>(instructions); | 123 Instr* instr = reinterpret_cast<Instr*>(instructions); |
115 for (int i = 0; i < instruction_count; i++) { | 124 for (int i = 0; i < instruction_count; i++) { |
116 *(pc + i) = *(instr + i); | 125 *(pc + i) = *(instr + i); |
117 } | 126 } |
118 | 127 |
119 // Indicate that code has changed. | 128 // Indicate that code has changed. |
120 CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize); | 129 CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize); |
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2261 | 2270 |
2262 // Since a constant pool was just emitted, move the check offset forward by | 2271 // Since a constant pool was just emitted, move the check offset forward by |
2263 // the standard interval. | 2272 // the standard interval. |
2264 next_buffer_check_ = pc_offset() + kCheckConstInterval; | 2273 next_buffer_check_ = pc_offset() + kCheckConstInterval; |
2265 } | 2274 } |
2266 | 2275 |
2267 | 2276 |
2268 } } // namespace v8::internal | 2277 } } // namespace v8::internal |
2269 | 2278 |
2270 #endif // V8_TARGET_ARCH_ARM && V8_ARM_VARIANT_ARM | 2279 #endif // V8_TARGET_ARCH_ARM && V8_ARM_VARIANT_ARM |
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