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| 1 /* linux/arch/arm/mach-s5pv210/include/mach/regs-hdmi.h |
| 2 * |
| 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 4 * http://www.samsung.com/ |
| 5 * |
| 6 * S5PV210 - Hdmi register header file for Samsung TVOut driver |
| 7 * |
| 8 * This program is free software; you can redistribute it and/or modify |
| 9 * it under the terms of the GNU General Public License version 2 as |
| 10 * published by the Free Software Foundation. |
| 11 */ |
| 12 |
| 13 #ifndef __ASM_ARCH_REGS_HDMI_H |
| 14 #define __ASM_ARCH_REGS_HDMI_H __FILE__ |
| 15 |
| 16 #define S5P_I2C_HDMI_PHY_BASE(x) (x) |
| 17 |
| 18 /* |
| 19 * HDMI PHY is configured through the dedicated I2C. |
| 20 * The dedicated I2C for HDMI PHY is only used as TX mode |
| 21 * I2C-BUS Interface for HDMI PHY is internally connected |
| 22 */ |
| 23 #define I2C_HDMI_CON S5P_I2C_HDMI_PHY_BASE(0x0000) |
| 24 #define I2C_HDMI_STAT S5P_I2C_HDMI_PHY_BASE(0x0004) |
| 25 #define I2C_HDMI_ADD S5P_I2C_HDMI_PHY_BASE(0x0008) |
| 26 #define I2C_HDMI_DS S5P_I2C_HDMI_PHY_BASE(0x000c) |
| 27 #define I2C_HDMI_LC S5P_I2C_HDMI_PHY_BASE(0x0010) |
| 28 |
| 29 |
| 30 #define S5P_HDMI_CTRL_BASE(x) (x) |
| 31 #define S5P_HDMI_BASE(x) (x + 0x00010000) |
| 32 #define S5P_HDMI_SPDIF_BASE(x) (x + 0x00030000) |
| 33 #define S5P_HDMI_I2S_BASE(x) (x + 0x00040000) |
| 34 #define S5P_HDMI_TG_BASE(x) (x + 0x00050000) |
| 35 #define S5P_HDMI_EFUSE_BASE(x) (x + 0x00060000) |
| 36 |
| 37 |
| 38 #define S5P_HDMI_CTRL_INTC_CON S5P_HDMI_CTRL_BASE(0x0000) |
| 39 #define S5P_HDMI_CTRL_INTC_FLAG S5P_HDMI_CTRL_BASE(0x0004) |
| 40 #define S5P_HDMI_CTRL_HDCP_KEY_LOAD S5P_HDMI_CTRL_BASE(0x0008) |
| 41 #define S5P_HDMI_CTRL_HPD S5P_HDMI_CTRL_BASE(0x000C) |
| 42 #define S5P_HDMI_CTRL_AUDIO_CLKSEL S5P_HDMI_CTRL_BASE(0x0010) |
| 43 #define S5P_HDMI_CTRL_PHY_RSTOUT S5P_HDMI_CTRL_BASE(0x0014) |
| 44 #define S5P_HDMI_CTRL_PHY_VPLL S5P_HDMI_CTRL_BASE(0x0018) |
| 45 #define S5P_HDMI_CTRL_PHY_CMU S5P_HDMI_CTRL_BASE(0x001C) |
| 46 #define S5P_HDMI_CTRL_CORE_RSTOUT S5P_HDMI_CTRL_BASE(0x0020) |
| 47 |
| 48 #define S5P_HDMI_CON_0 S5P_HDMI_BASE(0x0000) |
| 49 #define S5P_HDMI_CON_1 S5P_HDMI_BASE(0x0004) |
| 50 #define S5P_HDMI_CON_2 S5P_HDMI_BASE(0x0008) |
| 51 #define S5P_STATUS S5P_HDMI_BASE(0x0010) |
| 52 #define HDMI_PHY_STATUS S5P_HDMI_BASE(0x0014) |
| 53 #define S5P_STATUS_EN S5P_HDMI_BASE(0x0020) |
| 54 #define S5P_HPD S5P_HDMI_BASE(0x0030) |
| 55 #define S5P_MODE_SEL S5P_HDMI_BASE(0x0040) |
| 56 #define S5P_ENC_EN S5P_HDMI_BASE(0x0044) |
| 57 |
| 58 #define S5P_BLUE_SCREEN_0 S5P_HDMI_BASE(0x0050) |
| 59 #define S5P_BLUE_SCREEN_1 S5P_HDMI_BASE(0x0054) |
| 60 #define S5P_BLUE_SCREEN_2 S5P_HDMI_BASE(0x0058) |
| 61 |
| 62 #define S5P_HDMI_YMAX S5P_HDMI_BASE(0x0060) |
| 63 #define S5P_HDMI_YMIN S5P_HDMI_BASE(0x0064) |
| 64 #define S5P_HDMI_CMAX S5P_HDMI_BASE(0x0068) |
| 65 #define S5P_HDMI_CMIN S5P_HDMI_BASE(0x006C) |
| 66 |
| 67 #define S5P_H_BLANK_0 S5P_HDMI_BASE(0x00A0) |
| 68 #define S5P_H_BLANK_1 S5P_HDMI_BASE(0x00A4) |
| 69 #define S5P_V_BLANK_0 S5P_HDMI_BASE(0x00B0) |
| 70 #define S5P_V_BLANK_1 S5P_HDMI_BASE(0x00B4) |
| 71 #define S5P_V_BLANK_2 S5P_HDMI_BASE(0x00B8) |
| 72 #define S5P_H_V_LINE_0 S5P_HDMI_BASE(0x00C0) |
| 73 #define S5P_H_V_LINE_1 S5P_HDMI_BASE(0x00C4) |
| 74 #define S5P_H_V_LINE_2 S5P_HDMI_BASE(0x00C8) |
| 75 |
| 76 #define S5P_SYNC_MODE S5P_HDMI_BASE(0x00E4) |
| 77 #define S5P_INT_PRO_MODE S5P_HDMI_BASE(0x00E8) |
| 78 |
| 79 #define S5P_V_BLANK_F_0 S5P_HDMI_BASE(0x0110) |
| 80 #define S5P_V_BLANK_F_1 S5P_HDMI_BASE(0x0114) |
| 81 #define S5P_V_BLANK_F_2 S5P_HDMI_BASE(0x0118) |
| 82 #define S5P_H_SYNC_GEN_0 S5P_HDMI_BASE(0x0120) |
| 83 #define S5P_H_SYNC_GEN_1 S5P_HDMI_BASE(0x0124) |
| 84 #define S5P_H_SYNC_GEN_2 S5P_HDMI_BASE(0x0128) |
| 85 #define S5P_V_SYNC_GEN_1_0 S5P_HDMI_BASE(0x0130) |
| 86 #define S5P_V_SYNC_GEN_1_1 S5P_HDMI_BASE(0x0134) |
| 87 #define S5P_V_SYNC_GEN_1_2 S5P_HDMI_BASE(0x0138) |
| 88 #define S5P_V_SYNC_GEN_2_0 S5P_HDMI_BASE(0x0140) |
| 89 #define S5P_V_SYNC_GEN_2_1 S5P_HDMI_BASE(0x0144) |
| 90 #define S5P_V_SYNC_GEN_2_2 S5P_HDMI_BASE(0x0148) |
| 91 #define S5P_V_SYNC_GEN_3_0 S5P_HDMI_BASE(0x0150) |
| 92 #define S5P_V_SYNC_GEN_3_1 S5P_HDMI_BASE(0x0154) |
| 93 #define S5P_V_SYNC_GEN_3_2 S5P_HDMI_BASE(0x0158) |
| 94 |
| 95 #define S5P_ASP_CON S5P_HDMI_BASE(0x0160) |
| 96 #define S5P_ASP_SP_FLAT S5P_HDMI_BASE(0x0164) |
| 97 #define S5P_ASP_CHCFG0 S5P_HDMI_BASE(0x0170) |
| 98 #define S5P_ASP_CHCFG1 S5P_HDMI_BASE(0x0174) |
| 99 #define S5P_ASP_CHCFG2 S5P_HDMI_BASE(0x0178) |
| 100 #define S5P_ASP_CHCFG3 S5P_HDMI_BASE(0x017C) |
| 101 |
| 102 #define S5P_ACR_CON S5P_HDMI_BASE(0x0180) |
| 103 #define S5P_ACR_MCTS0 S5P_HDMI_BASE(0x0184) |
| 104 #define S5P_ACR_MCTS1 S5P_HDMI_BASE(0x0188) |
| 105 #define S5P_ACR_MCTS2 S5P_HDMI_BASE(0x018C) |
| 106 #define S5P_ACR_CTS0 S5P_HDMI_BASE(0x0190) |
| 107 #define S5P_ACR_CTS1 S5P_HDMI_BASE(0x0194) |
| 108 #define S5P_ACR_CTS2 S5P_HDMI_BASE(0x0198) |
| 109 #define S5P_ACR_N0 S5P_HDMI_BASE(0x01A0) |
| 110 #define S5P_ACR_N1 S5P_HDMI_BASE(0x01A4) |
| 111 #define S5P_ACR_N2 S5P_HDMI_BASE(0x01A8) |
| 112 #define S5P_ACR_LSB2 S5P_HDMI_BASE(0x01B0) |
| 113 #define S5P_ACR_TXCNT S5P_HDMI_BASE(0x01B4) |
| 114 #define S5P_ACR_TXINTERVAL S5P_HDMI_BASE(0x01B8) |
| 115 #define S5P_ACR_CTS_OFFSET S5P_HDMI_BASE(0x01BC) |
| 116 |
| 117 #define S5P_GCP_CON S5P_HDMI_BASE(0x01C0) |
| 118 #define S5P_GCP_BYTE1 S5P_HDMI_BASE(0x01D0) |
| 119 #define S5P_GCP_BYTE2 S5P_HDMI_BASE(0x01D4) |
| 120 #define S5P_GCP_BYTE3 S5P_HDMI_BASE(0x01D8) |
| 121 |
| 122 #define S5P_ACP_CON S5P_HDMI_BASE(0x01E0) |
| 123 #define S5P_ACP_TYPE S5P_HDMI_BASE(0x01E4) |
| 124 |
| 125 #define S5P_ACP_DATA0 S5P_HDMI_BASE(0x0200) |
| 126 #define S5P_ACP_DATA1 S5P_HDMI_BASE(0x0204) |
| 127 #define S5P_ACP_DATA2 S5P_HDMI_BASE(0x0208) |
| 128 #define S5P_ACP_DATA3 S5P_HDMI_BASE(0x020c) |
| 129 #define S5P_ACP_DATA4 S5P_HDMI_BASE(0x0210) |
| 130 #define S5P_ACP_DATA5 S5P_HDMI_BASE(0x0214) |
| 131 #define S5P_ACP_DATA6 S5P_HDMI_BASE(0x0218) |
| 132 #define S5P_ACP_DATA7 S5P_HDMI_BASE(0x021c) |
| 133 #define S5P_ACP_DATA8 S5P_HDMI_BASE(0x0220) |
| 134 #define S5P_ACP_DATA9 S5P_HDMI_BASE(0x0224) |
| 135 #define S5P_ACP_DATA10 S5P_HDMI_BASE(0x0228) |
| 136 #define S5P_ACP_DATA11 S5P_HDMI_BASE(0x022c) |
| 137 #define S5P_ACP_DATA12 S5P_HDMI_BASE(0x0230) |
| 138 #define S5P_ACP_DATA13 S5P_HDMI_BASE(0x0234) |
| 139 #define S5P_ACP_DATA14 S5P_HDMI_BASE(0x0238) |
| 140 #define S5P_ACP_DATA15 S5P_HDMI_BASE(0x023c) |
| 141 #define S5P_ACP_DATA16 S5P_HDMI_BASE(0x0240) |
| 142 |
| 143 #define S5P_ISRC_CON S5P_HDMI_BASE(0x0250) |
| 144 #define S5P_ISRC1_HEADER1 S5P_HDMI_BASE(0x0264) |
| 145 |
| 146 #define S5P_ISRC1_DATA0 S5P_HDMI_BASE(0x0270) |
| 147 #define S5P_ISRC1_DATA1 S5P_HDMI_BASE(0x0274) |
| 148 #define S5P_ISRC1_DATA2 S5P_HDMI_BASE(0x0278) |
| 149 #define S5P_ISRC1_DATA3 S5P_HDMI_BASE(0x027c) |
| 150 #define S5P_ISRC1_DATA4 S5P_HDMI_BASE(0x0280) |
| 151 #define S5P_ISRC1_DATA5 S5P_HDMI_BASE(0x0284) |
| 152 #define S5P_ISRC1_DATA6 S5P_HDMI_BASE(0x0288) |
| 153 #define S5P_ISRC1_DATA7 S5P_HDMI_BASE(0x028c) |
| 154 #define S5P_ISRC1_DATA8 S5P_HDMI_BASE(0x0290) |
| 155 #define S5P_ISRC1_DATA9 S5P_HDMI_BASE(0x0294) |
| 156 #define S5P_ISRC1_DATA10 S5P_HDMI_BASE(0x0298) |
| 157 #define S5P_ISRC1_DATA11 S5P_HDMI_BASE(0x029c) |
| 158 #define S5P_ISRC1_DATA12 S5P_HDMI_BASE(0x02a0) |
| 159 #define S5P_ISRC1_DATA13 S5P_HDMI_BASE(0x02a4) |
| 160 #define S5P_ISRC1_DATA14 S5P_HDMI_BASE(0x02a8) |
| 161 #define S5P_ISRC1_DATA15 S5P_HDMI_BASE(0x02ac) |
| 162 |
| 163 #define S5P_ISRC2_DATA0 S5P_HDMI_BASE(0x02b0) |
| 164 #define S5P_ISRC2_DATA1 S5P_HDMI_BASE(0x02b4) |
| 165 #define S5P_ISRC2_DATA2 S5P_HDMI_BASE(0x02b8) |
| 166 #define S5P_ISRC2_DATA3 S5P_HDMI_BASE(0x02bc) |
| 167 #define S5P_ISRC2_DATA4 S5P_HDMI_BASE(0x02c0) |
| 168 #define S5P_ISRC2_DATA5 S5P_HDMI_BASE(0x02c4) |
| 169 #define S5P_ISRC2_DATA6 S5P_HDMI_BASE(0x02c8) |
| 170 #define S5P_ISRC2_DATA7 S5P_HDMI_BASE(0x02cc) |
| 171 #define S5P_ISRC2_DATA8 S5P_HDMI_BASE(0x02d0) |
| 172 #define S5P_ISRC2_DATA9 S5P_HDMI_BASE(0x02d4) |
| 173 #define S5P_ISRC2_DATA10 S5P_HDMI_BASE(0x02d8) |
| 174 #define S5P_ISRC2_DATA11 S5P_HDMI_BASE(0x02dc) |
| 175 #define S5P_ISRC2_DATA12 S5P_HDMI_BASE(0x02e0) |
| 176 #define S5P_ISRC2_DATA13 S5P_HDMI_BASE(0x02e4) |
| 177 #define S5P_ISRC2_DATA14 S5P_HDMI_BASE(0x02e8) |
| 178 #define S5P_ISRC2_DATA15 S5P_HDMI_BASE(0x02ec) |
| 179 |
| 180 #define S5P_AVI_CON S5P_HDMI_BASE(0x0300) |
| 181 #define S5P_AVI_CHECK_SUM S5P_HDMI_BASE(0x0310) |
| 182 |
| 183 #define S5P_AVI_BYTE1 S5P_HDMI_BASE(0x0320) |
| 184 #define S5P_AVI_BYTE2 S5P_HDMI_BASE(0x0324) |
| 185 #define S5P_AVI_BYTE3 S5P_HDMI_BASE(0x0328) |
| 186 #define S5P_AVI_BYTE4 S5P_HDMI_BASE(0x032c) |
| 187 #define S5P_AVI_BYTE5 S5P_HDMI_BASE(0x0330) |
| 188 #define S5P_AVI_BYTE6 S5P_HDMI_BASE(0x0334) |
| 189 #define S5P_AVI_BYTE7 S5P_HDMI_BASE(0x0338) |
| 190 #define S5P_AVI_BYTE8 S5P_HDMI_BASE(0x033c) |
| 191 #define S5P_AVI_BYTE9 S5P_HDMI_BASE(0x0340) |
| 192 #define S5P_AVI_BYTE10 S5P_HDMI_BASE(0x0344) |
| 193 #define S5P_AVI_BYTE11 S5P_HDMI_BASE(0x0348) |
| 194 #define S5P_AVI_BYTE12 S5P_HDMI_BASE(0x034c) |
| 195 #define S5P_AVI_BYTE13 S5P_HDMI_BASE(0x0350) |
| 196 |
| 197 #define S5P_AUI_CON S5P_HDMI_BASE(0x0360) |
| 198 #define S5P_AUI_CHECK_SUM S5P_HDMI_BASE(0x0370) |
| 199 |
| 200 #define S5P_AUI_BYTE1 S5P_HDMI_BASE(0x0380) |
| 201 #define S5P_AUI_BYTE2 S5P_HDMI_BASE(0x0384) |
| 202 #define S5P_AUI_BYTE3 S5P_HDMI_BASE(0x0388) |
| 203 #define S5P_AUI_BYTE4 S5P_HDMI_BASE(0x038c) |
| 204 #define S5P_AUI_BYTE5 S5P_HDMI_BASE(0x0390) |
| 205 |
| 206 #define S5P_MPG_CON S5P_HDMI_BASE(0x03A0) |
| 207 #define S5P_MPG_CHECK_SUM S5P_HDMI_BASE(0x03B0) |
| 208 |
| 209 #define S5P_MPEG_BYTE1 S5P_HDMI_BASE(0x03c0) |
| 210 #define S5P_MPEG_BYTE2 S5P_HDMI_BASE(0x03c4) |
| 211 #define S5P_MPEG_BYTE3 S5P_HDMI_BASE(0x03c8) |
| 212 #define S5P_MPEG_BYTE4 S5P_HDMI_BASE(0x03cc) |
| 213 #define S5P_MPEG_BYTE5 S5P_HDMI_BASE(0x03d0) |
| 214 |
| 215 #define S5P_SPD_CON S5P_HDMI_BASE(0x0400) |
| 216 #define S5P_SPD_HEADER0 S5P_HDMI_BASE(0x0410) |
| 217 #define S5P_SPD_HEADER1 S5P_HDMI_BASE(0x0414) |
| 218 #define S5P_SPD_HEADER2 S5P_HDMI_BASE(0x0418) |
| 219 |
| 220 #define S5P_SPD_DATA0 S5P_HDMI_BASE(0x0420) |
| 221 #define S5P_SPD_DATA1 S5P_HDMI_BASE(0x0424) |
| 222 #define S5P_SPD_DATA2 S5P_HDMI_BASE(0x0428) |
| 223 #define S5P_SPD_DATA3 S5P_HDMI_BASE(0x042c) |
| 224 #define S5P_SPD_DATA4 S5P_HDMI_BASE(0x0430) |
| 225 #define S5P_SPD_DATA5 S5P_HDMI_BASE(0x0434) |
| 226 #define S5P_SPD_DATA6 S5P_HDMI_BASE(0x0438) |
| 227 #define S5P_SPD_DATA7 S5P_HDMI_BASE(0x043c) |
| 228 #define S5P_SPD_DATA8 S5P_HDMI_BASE(0x0440) |
| 229 #define S5P_SPD_DATA9 S5P_HDMI_BASE(0x0444) |
| 230 #define S5P_SPD_DATA10 S5P_HDMI_BASE(0x0448) |
| 231 #define S5P_SPD_DATA11 S5P_HDMI_BASE(0x044c) |
| 232 #define S5P_SPD_DATA12 S5P_HDMI_BASE(0x0450) |
| 233 #define S5P_SPD_DATA13 S5P_HDMI_BASE(0x0454) |
| 234 #define S5P_SPD_DATA14 S5P_HDMI_BASE(0x0458) |
| 235 #define S5P_SPD_DATA15 S5P_HDMI_BASE(0x045c) |
| 236 #define S5P_SPD_DATA16 S5P_HDMI_BASE(0x0460) |
| 237 #define S5P_SPD_DATA17 S5P_HDMI_BASE(0x0464) |
| 238 #define S5P_SPD_DATA18 S5P_HDMI_BASE(0x0468) |
| 239 #define S5P_SPD_DATA19 S5P_HDMI_BASE(0x046c) |
| 240 #define S5P_SPD_DATA20 S5P_HDMI_BASE(0x0470) |
| 241 #define S5P_SPD_DATA21 S5P_HDMI_BASE(0x0474) |
| 242 #define S5P_SPD_DATA22 S5P_HDMI_BASE(0x0478) |
| 243 #define S5P_SPD_DATA23 S5P_HDMI_BASE(0x048c) |
| 244 #define S5P_SPD_DATA24 S5P_HDMI_BASE(0x0480) |
| 245 #define S5P_SPD_DATA25 S5P_HDMI_BASE(0x0484) |
| 246 #define S5P_SPD_DATA26 S5P_HDMI_BASE(0x0488) |
| 247 #define S5P_SPD_DATA27 S5P_HDMI_BASE(0x048c) |
| 248 |
| 249 #define S5P_HDCP_RX_SHA1_0_0 S5P_HDMI_BASE(0x0600) |
| 250 #define S5P_HDCP_RX_SHA1_0_1 S5P_HDMI_BASE(0x0604) |
| 251 #define S5P_HDCP_RX_SHA1_0_2 S5P_HDMI_BASE(0x0608) |
| 252 #define S5P_HDCP_RX_SHA1_0_3 S5P_HDMI_BASE(0x060C) |
| 253 #define S5P_HDCP_RX_SHA1_1_0 S5P_HDMI_BASE(0x0610) |
| 254 #define S5P_HDCP_RX_SHA1_1_1 S5P_HDMI_BASE(0x0614) |
| 255 #define S5P_HDCP_RX_SHA1_1_2 S5P_HDMI_BASE(0x0618) |
| 256 #define S5P_HDCP_RX_SHA1_1_3 S5P_HDMI_BASE(0x061C) |
| 257 #define S5P_HDCP_RX_SHA1_2_0 S5P_HDMI_BASE(0x0620) |
| 258 #define S5P_HDCP_RX_SHA1_2_1 S5P_HDMI_BASE(0x0624) |
| 259 #define S5P_HDCP_RX_SHA1_2_2 S5P_HDMI_BASE(0x0628) |
| 260 #define S5P_HDCP_RX_SHA1_2_3 S5P_HDMI_BASE(0x062C) |
| 261 #define S5P_HDCP_RX_SHA1_3_0 S5P_HDMI_BASE(0x0630) |
| 262 #define S5P_HDCP_RX_SHA1_3_1 S5P_HDMI_BASE(0x0634) |
| 263 #define S5P_HDCP_RX_SHA1_3_2 S5P_HDMI_BASE(0x0638) |
| 264 #define S5P_HDCP_RX_SHA1_3_3 S5P_HDMI_BASE(0x063C) |
| 265 #define S5P_HDCP_RX_SHA1_4_0 S5P_HDMI_BASE(0x0640) |
| 266 #define S5P_HDCP_RX_SHA1_4_1 S5P_HDMI_BASE(0x0644) |
| 267 #define S5P_HDCP_RX_SHA1_4_2 S5P_HDMI_BASE(0x0648) |
| 268 #define S5P_HDCP_RX_SHA1_4_3 S5P_HDMI_BASE(0x064C) |
| 269 |
| 270 #define S5P_HDCP_RX_KSV_0_0 S5P_HDMI_BASE(0x0650) |
| 271 #define S5P_HDCP_RX_KSV_0_1 S5P_HDMI_BASE(0x0654) |
| 272 #define S5P_HDCP_RX_KSV_0_2 S5P_HDMI_BASE(0x0658) |
| 273 #define S5P_HDCP_RX_KSV_0_3 S5P_HDMI_BASE(0x065C) |
| 274 #define S5P_HDCP_RX_KSV_0_4 S5P_HDMI_BASE(0x0660) |
| 275 |
| 276 #define S5P_HDCP_RX_KSV_LIST_CTRL S5P_HDMI_BASE(0x0664) |
| 277 #define S5P_HDCP_AUTH_STATUS S5P_HDMI_BASE(0x0670) |
| 278 #define S5P_HDCP_CTRL1 S5P_HDMI_BASE(0x0680) |
| 279 #define S5P_HDCP_CTRL2 S5P_HDMI_BASE(0x0684) |
| 280 #define S5P_HDCP_CHECK_RESULT S5P_HDMI_BASE(0x0690) |
| 281 |
| 282 #define S5P_HDCP_BKSV_0_0 S5P_HDMI_BASE(0x06A0) |
| 283 #define S5P_HDCP_BKSV_0_1 S5P_HDMI_BASE(0x06A4) |
| 284 #define S5P_HDCP_BKSV_0_2 S5P_HDMI_BASE(0x06A8) |
| 285 #define S5P_HDCP_BKSV_0_3 S5P_HDMI_BASE(0x06AC) |
| 286 #define S5P_HDCP_BKSV_1 S5P_HDMI_BASE(0x06B0) |
| 287 |
| 288 #define S5P_HDCP_AKSV_0_0 S5P_HDMI_BASE(0x06C0) |
| 289 #define S5P_HDCP_AKSV_0_1 S5P_HDMI_BASE(0x06C4) |
| 290 #define S5P_HDCP_AKSV_0_2 S5P_HDMI_BASE(0x06C8) |
| 291 #define S5P_HDCP_AKSV_0_3 S5P_HDMI_BASE(0x06CC) |
| 292 #define S5P_HDCP_AKSV_1 S5P_HDMI_BASE(0x06D0) |
| 293 |
| 294 #define S5P_HDCP_An_0_0 S5P_HDMI_BASE(0x06E0) |
| 295 #define S5P_HDCP_An_0_1 S5P_HDMI_BASE(0x06E4) |
| 296 #define S5P_HDCP_An_0_2 S5P_HDMI_BASE(0x06E8) |
| 297 #define S5P_HDCP_An_0_3 S5P_HDMI_BASE(0x06EC) |
| 298 #define S5P_HDCP_An_1_0 S5P_HDMI_BASE(0x06F0) |
| 299 #define S5P_HDCP_An_1_1 S5P_HDMI_BASE(0x06F4) |
| 300 #define S5P_HDCP_An_1_2 S5P_HDMI_BASE(0x06F8) |
| 301 #define S5P_HDCP_An_1_3 S5P_HDMI_BASE(0x06FC) |
| 302 |
| 303 #define S5P_HDCP_BCAPS S5P_HDMI_BASE(0x0700) |
| 304 #define S5P_HDCP_BSTATUS_0 S5P_HDMI_BASE(0x0710) |
| 305 #define S5P_HDCP_BSTATUS_1 S5P_HDMI_BASE(0x0714) |
| 306 #define S5P_HDCP_Ri_0 S5P_HDMI_BASE(0x0740) |
| 307 #define S5P_HDCP_Ri_1 S5P_HDMI_BASE(0x0744) |
| 308 |
| 309 #define S5P_HDCP_I2C_INT S5P_HDMI_BASE(0x0780) |
| 310 #define S5P_HDCP_AN_INT S5P_HDMI_BASE(0x0790) |
| 311 #define S5P_HDCP_WDT_INT S5P_HDMI_BASE(0x07a0) |
| 312 #define S5P_HDCP_RI_INT S5P_HDMI_BASE(0x07b0) |
| 313 |
| 314 #define S5P_HDCP_RI_COMPARE_0 S5P_HDMI_BASE(0x07d0) |
| 315 #define S5P_HDCP_RI_COMPARE_1 S5P_HDMI_BASE(0x07d4) |
| 316 #define S5P_HDCP_FRAME_COUNT S5P_HDMI_BASE(0x07e0) |
| 317 |
| 318 #define HDMI_GAMUT_CON S5P_HDMI_BASE(0x0500) |
| 319 #define HDMI_GAMUT_HEADER0 S5P_HDMI_BASE(0x0504) |
| 320 #define HDMI_GAMUT_HEADER1 S5P_HDMI_BASE(0x0508) |
| 321 #define HDMI_GAMUT_HEADER2 S5P_HDMI_BASE(0x050c) |
| 322 #define HDMI_GAMUT_DATA00 S5P_HDMI_BASE(0x0510) |
| 323 #define HDMI_GAMUT_DATA01 S5P_HDMI_BASE(0x0514) |
| 324 #define HDMI_GAMUT_DATA02 S5P_HDMI_BASE(0x0518) |
| 325 #define HDMI_GAMUT_DATA03 S5P_HDMI_BASE(0x051c) |
| 326 #define HDMI_GAMUT_DATA04 S5P_HDMI_BASE(0x0520) |
| 327 #define HDMI_GAMUT_DATA05 S5P_HDMI_BASE(0x0524) |
| 328 #define HDMI_GAMUT_DATA06 S5P_HDMI_BASE(0x0528) |
| 329 #define HDMI_GAMUT_DATA07 S5P_HDMI_BASE(0x052c) |
| 330 #define HDMI_GAMUT_DATA08 S5P_HDMI_BASE(0x0530) |
| 331 #define HDMI_GAMUT_DATA09 S5P_HDMI_BASE(0x0534) |
| 332 #define HDMI_GAMUT_DATA10 S5P_HDMI_BASE(0x0538) |
| 333 #define HDMI_GAMUT_DATA11 S5P_HDMI_BASE(0x053c) |
| 334 #define HDMI_GAMUT_DATA12 S5P_HDMI_BASE(0x0540) |
| 335 #define HDMI_GAMUT_DATA13 S5P_HDMI_BASE(0x0544) |
| 336 #define HDMI_GAMUT_DATA14 S5P_HDMI_BASE(0x0548) |
| 337 #define HDMI_GAMUT_DATA15 S5P_HDMI_BASE(0x054c) |
| 338 #define HDMI_GAMUT_DATA16 S5P_HDMI_BASE(0x0550) |
| 339 #define HDMI_GAMUT_DATA17 S5P_HDMI_BASE(0x0554) |
| 340 #define HDMI_GAMUT_DATA18 S5P_HDMI_BASE(0x0558) |
| 341 #define HDMI_GAMUT_DATA19 S5P_HDMI_BASE(0x055c) |
| 342 #define HDMI_GAMUT_DATA20 S5P_HDMI_BASE(0x0560) |
| 343 #define HDMI_GAMUT_DATA21 S5P_HDMI_BASE(0x0564) |
| 344 #define HDMI_GAMUT_DATA22 S5P_HDMI_BASE(0x0568) |
| 345 #define HDMI_GAMUT_DATA23 S5P_HDMI_BASE(0x056c) |
| 346 #define HDMI_GAMUT_DATA24 S5P_HDMI_BASE(0x0570) |
| 347 #define HDMI_GAMUT_DATA25 S5P_HDMI_BASE(0x0574) |
| 348 #define HDMI_GAMUT_DATA26 S5P_HDMI_BASE(0x0578) |
| 349 #define HDMI_GAMUT_DATA27 S5P_HDMI_BASE(0x057c) |
| 350 |
| 351 #define S5P_HDMI_DC_CONTROL S5P_HDMI_BASE(0x05C0) |
| 352 #define S5P_HDMI_VIDEO_PATTERN_GEN S5P_HDMI_BASE(0x05C4) |
| 353 #define S5P_HDMI_HPD_GEN S5P_HDMI_BASE(0x05C8) |
| 354 |
| 355 #define S5P_TG_CMD S5P_HDMI_TG_BASE(0x0000) |
| 356 #define S5P_TG_H_FSZ_L S5P_HDMI_TG_BASE(0x0018) |
| 357 #define S5P_TG_H_FSZ_H S5P_HDMI_TG_BASE(0x001C) |
| 358 #define S5P_TG_HACT_ST_L S5P_HDMI_TG_BASE(0x0020) |
| 359 #define S5P_TG_HACT_ST_H S5P_HDMI_TG_BASE(0x0024) |
| 360 #define S5P_TG_HACT_SZ_L S5P_HDMI_TG_BASE(0x0028) |
| 361 #define S5P_TG_HACT_SZ_H S5P_HDMI_TG_BASE(0x002C) |
| 362 #define S5P_TG_V_FSZ_L S5P_HDMI_TG_BASE(0x0030) |
| 363 #define S5P_TG_V_FSZ_H S5P_HDMI_TG_BASE(0x0034) |
| 364 #define S5P_TG_VSYNC_L S5P_HDMI_TG_BASE(0x0038) |
| 365 #define S5P_TG_VSYNC_H S5P_HDMI_TG_BASE(0x003C) |
| 366 #define S5P_TG_VSYNC2_L S5P_HDMI_TG_BASE(0x0040) |
| 367 #define S5P_TG_VSYNC2_H S5P_HDMI_TG_BASE(0x0044) |
| 368 #define S5P_TG_VACT_ST_L S5P_HDMI_TG_BASE(0x0048) |
| 369 #define S5P_TG_VACT_ST_H S5P_HDMI_TG_BASE(0x004C) |
| 370 #define S5P_TG_VACT_SZ_L S5P_HDMI_TG_BASE(0x0050) |
| 371 #define S5P_TG_VACT_SZ_H S5P_HDMI_TG_BASE(0x0054) |
| 372 #define S5P_TG_FIELD_CHG_L S5P_HDMI_TG_BASE(0x0058) |
| 373 #define S5P_TG_FIELD_CHG_H S5P_HDMI_TG_BASE(0x005C) |
| 374 #define S5P_TG_VACT_ST2_L S5P_HDMI_TG_BASE(0x0060) |
| 375 #define S5P_TG_VACT_ST2_H S5P_HDMI_TG_BASE(0x0064) |
| 376 |
| 377 #define S5P_TG_VSYNC_TOP_HDMI_L S5P_HDMI_TG_BASE(0x0078) |
| 378 #define S5P_TG_VSYNC_TOP_HDMI_H S5P_HDMI_TG_BASE(0x007C) |
| 379 #define S5P_TG_VSYNC_BOT_HDMI_L S5P_HDMI_TG_BASE(0x0080) |
| 380 #define S5P_TG_VSYNC_BOT_HDMI_H S5P_HDMI_TG_BASE(0x0084) |
| 381 #define S5P_TG_FIELD_TOP_HDMI_L S5P_HDMI_TG_BASE(0x0088) |
| 382 #define S5P_TG_FIELD_TOP_HDMI_H S5P_HDMI_TG_BASE(0x008C) |
| 383 #define S5P_TG_FIELD_BOT_HDMI_L S5P_HDMI_TG_BASE(0x0090) |
| 384 #define S5P_TG_FIELD_BOT_HDMI_H S5P_HDMI_TG_BASE(0x0094) |
| 385 |
| 386 #define S5P_EFUSE_CTRL S5P_HDMI_EFUSE_BASE(0x0000) |
| 387 #define S5P_EFUSE_STATUS S5P_HDMI_EFUSE_BASE(0x0004) |
| 388 #define S5P_EFUSE_ADDR_WIDTH S5P_HDMI_EFUSE_BASE(0x0008) |
| 389 #define S5P_EFUSE_SIGDEV_ASSERT S5P_HDMI_EFUSE_BASE(0x000c) |
| 390 #define S5P_EFUSE_SIGDEV_DEASSERT S5P_HDMI_EFUSE_BASE(0x0010) |
| 391 #define S5P_EFUSE_PRCHG_ASSERT S5P_HDMI_EFUSE_BASE(0x0014) |
| 392 #define S5P_EFUSE_PRCHG_DEASSERT S5P_HDMI_EFUSE_BASE(0x0018) |
| 393 #define S5P_EFUSE_FSET_ASSERT S5P_HDMI_EFUSE_BASE(0x001c) |
| 394 #define S5P_EFUSE_FSET_DEASSERT S5P_HDMI_EFUSE_BASE(0x0020) |
| 395 #define S5P_EFUSE_SENSING S5P_HDMI_EFUSE_BASE(0x0024) |
| 396 #define S5P_EFUSE_SCK_ASSERT S5P_HDMI_EFUSE_BASE(0x0028) |
| 397 #define S5P_EFUSE_SCK_DEASSERT S5P_HDMI_EFUSE_BASE(0x002c) |
| 398 #define S5P_EFUSE_SDOUT_OFFSET S5P_HDMI_EFUSE_BASE(0x0030) |
| 399 #define S5P_EFUSE_READ_OFFSET S5P_HDMI_EFUSE_BASE(0x0034) |
| 400 |
| 401 #define S5P_HDMI_I2S_CLK_CON S5P_HDMI_I2S_BASE(0x0000) |
| 402 #define S5P_HDMI_I2S_CON_1 S5P_HDMI_I2S_BASE(0x0004) |
| 403 #define S5P_HDMI_I2S_CON_2 S5P_HDMI_I2S_BASE(0x0008) |
| 404 #define S5P_HDMI_I2S_PIN_SEL_0 S5P_HDMI_I2S_BASE(0x000C) |
| 405 #define S5P_HDMI_I2S_PIN_SEL_1 S5P_HDMI_I2S_BASE(0x0010) |
| 406 #define S5P_HDMI_I2S_PIN_SEL_2 S5P_HDMI_I2S_BASE(0x0014) |
| 407 #define S5P_HDMI_I2S_PIN_SEL_3 S5P_HDMI_I2S_BASE(0x0018) |
| 408 #define S5P_HDMI_I2S_DSD_CON S5P_HDMI_I2S_BASE(0x001C) |
| 409 #define S5P_HDMI_I2S_MUX_CON S5P_HDMI_I2S_BASE(0x0020) |
| 410 #define S5P_HDMI_I2S_CH_ST_CON S5P_HDMI_I2S_BASE(0x0024) |
| 411 #define S5P_HDMI_I2S_CH_ST_0 S5P_HDMI_I2S_BASE(0x0028) |
| 412 #define S5P_HDMI_I2S_CH_ST_1 S5P_HDMI_I2S_BASE(0x002C) |
| 413 #define S5P_HDMI_I2S_CH_ST_2 S5P_HDMI_I2S_BASE(0x0030) |
| 414 #define S5P_HDMI_I2S_CH_ST_3 S5P_HDMI_I2S_BASE(0x0034) |
| 415 #define S5P_HDMI_I2S_CH_ST_4 S5P_HDMI_I2S_BASE(0x0038) |
| 416 #define S5P_HDMI_I2S_CH_ST_SH_0 S5P_HDMI_I2S_BASE(0x003C) |
| 417 #define S5P_HDMI_I2S_CH_ST_SH_1 S5P_HDMI_I2S_BASE(0x0040) |
| 418 #define S5P_HDMI_I2S_CH_ST_SH_2 S5P_HDMI_I2S_BASE(0x0044) |
| 419 #define S5P_HDMI_I2S_CH_ST_SH_3 S5P_HDMI_I2S_BASE(0x0048) |
| 420 #define S5P_HDMI_I2S_CH_ST_SH_4 S5P_HDMI_I2S_BASE(0x004C) |
| 421 #define S5P_HDMI_I2S_VD_DATA S5P_HDMI_I2S_BASE(0x0050) |
| 422 #define S5P_HDMI_I2S_MUX_CH S5P_HDMI_I2S_BASE(0x0054) |
| 423 #define S5P_HDMI_I2S_MUX_CUV S5P_HDMI_I2S_BASE(0x0058) |
| 424 #define S5P_HDMI_I2S_IRQ_MASK S5P_HDMI_I2S_BASE(0x005C) |
| 425 #define S5P_HDMI_I2S_IRQ_STATUS S5P_HDMI_I2S_BASE(0x0060) |
| 426 #define S5P_HDMI_I2S_CH0_L_0 S5P_HDMI_I2S_BASE(0x0064) |
| 427 #define S5P_HDMI_I2S_CH0_L_1 S5P_HDMI_I2S_BASE(0x0068) |
| 428 #define S5P_HDMI_I2S_CH0_L_2 S5P_HDMI_I2S_BASE(0x006C) |
| 429 #define S5P_HDMI_I2S_CH0_L_3 S5P_HDMI_I2S_BASE(0x0070) |
| 430 #define S5P_HDMI_I2S_CH0_R_0 S5P_HDMI_I2S_BASE(0x0074) |
| 431 #define S5P_HDMI_I2S_CH0_R_1 S5P_HDMI_I2S_BASE(0x0078) |
| 432 #define S5P_HDMI_I2S_CH0_R_2 S5P_HDMI_I2S_BASE(0x007C) |
| 433 #define S5P_HDMI_I2S_CH0_R_3 S5P_HDMI_I2S_BASE(0x0080) |
| 434 #define S5P_HDMI_I2S_CH1_L_0 S5P_HDMI_I2S_BASE(0x0084) |
| 435 #define S5P_HDMI_I2S_CH1_L_1 S5P_HDMI_I2S_BASE(0x0088) |
| 436 #define S5P_HDMI_I2S_CH1_L_2 S5P_HDMI_I2S_BASE(0x008C) |
| 437 #define S5P_HDMI_I2S_CH1_L_3 S5P_HDMI_I2S_BASE(0x0090) |
| 438 #define S5P_HDMI_I2S_CH1_R_0 S5P_HDMI_I2S_BASE(0x0094) |
| 439 #define S5P_HDMI_I2S_CH1_R_1 S5P_HDMI_I2S_BASE(0x0098) |
| 440 #define S5P_HDMI_I2S_CH1_R_2 S5P_HDMI_I2S_BASE(0x009C) |
| 441 #define S5P_HDMI_I2S_CH1_R_3 S5P_HDMI_I2S_BASE(0x00A0) |
| 442 #define S5P_HDMI_I2S_CH2_L_0 S5P_HDMI_I2S_BASE(0x00A4) |
| 443 #define S5P_HDMI_I2S_CH2_L_1 S5P_HDMI_I2S_BASE(0x00A8) |
| 444 #define S5P_HDMI_I2S_CH2_L_2 S5P_HDMI_I2S_BASE(0x00AC) |
| 445 #define S5P_HDMI_I2S_CH2_L_3 S5P_HDMI_I2S_BASE(0x00B0) |
| 446 #define S5P_HDMI_I2S_CH2_R_0 S5P_HDMI_I2S_BASE(0x00B4) |
| 447 #define S5P_HDMI_I2S_CH2_R_1 S5P_HDMI_I2S_BASE(0x00B8) |
| 448 #define S5P_HDMI_I2S_CH2_R_2 S5P_HDMI_I2S_BASE(0x00BC) |
| 449 #define S5P_HDMI_I2S_Ch2_R_3 S5P_HDMI_I2S_BASE(0x00C0) |
| 450 #define S5P_HDMI_I2S_CH3_L_0 S5P_HDMI_I2S_BASE(0x00C4) |
| 451 #define S5P_HDMI_I2S_CH3_L_1 S5P_HDMI_I2S_BASE(0x00C8) |
| 452 #define S5P_HDMI_I2S_CH3_L_2 S5P_HDMI_I2S_BASE(0x00CC) |
| 453 #define S5P_HDMI_I2S_CH3_R_0 S5P_HDMI_I2S_BASE(0x00D0) |
| 454 #define S5P_HDMI_I2S_CH3_R_1 S5P_HDMI_I2S_BASE(0x00D4) |
| 455 #define S5P_HDMI_I2S_CH3_R_2 S5P_HDMI_I2S_BASE(0x00D8) |
| 456 #define S5P_HDMI_I2S_CUV_L_R S5P_HDMI_I2S_BASE(0x00DC) |
| 457 |
| 458 #define S5P_SPDIFIN_CLK_CTRL S5P_HDMI_SPDIF_BASE(0x0000) |
| 459 #define S5P_SPDIFIN_OP_CTRL S5P_HDMI_SPDIF_BASE(0x0004) |
| 460 #define S5P_SPDIFIN_IRQ_MASK S5P_HDMI_SPDIF_BASE(0x0008) |
| 461 #define S5P_SPDIFIN_IRQ_STATUS S5P_HDMI_SPDIF_BASE(0x000C) |
| 462 #define S5P_SPDIFIN_CONFIG_1 S5P_HDMI_SPDIF_BASE(0x0010) |
| 463 #define S5P_SPDIFIN_CONFIG_2 S5P_HDMI_SPDIF_BASE(0x0014) |
| 464 #define S5P_SPDIFIN_USER_VALUE_1 S5P_HDMI_SPDIF_BASE(0x0020) |
| 465 #define S5P_SPDIFIN_USER_VALUE_2 S5P_HDMI_SPDIF_BASE(0x0024) |
| 466 #define S5P_SPDIFIN_USER_VALUE_3 S5P_HDMI_SPDIF_BASE(0x0028) |
| 467 #define S5P_SPDIFIN_USER_VALUE_4 S5P_HDMI_SPDIF_BASE(0x002C) |
| 468 #define S5P_SPDIFIN_CH_STATUS_0_1 S5P_HDMI_SPDIF_BASE(0x0030) |
| 469 #define S5P_SPDIFIN_CH_STATUS_0_2 S5P_HDMI_SPDIF_BASE(0x0034) |
| 470 #define S5P_SPDIFIN_CH_STATUS_0_3 S5P_HDMI_SPDIF_BASE(0x0038) |
| 471 #define S5P_SPDIFIN_CH_STATUS_0_4 S5P_HDMI_SPDIF_BASE(0x003C) |
| 472 #define S5P_SPDIFIN_CH_STATUS_1 S5P_HDMI_SPDIF_BASE(0x0040) |
| 473 #define S5P_SPDIFIN_FRAME_PERIOD_1 S5P_HDMI_SPDIF_BASE(0x0048) |
| 474 #define S5P_SPDIFIN_FRAME_PERIOD_2 S5P_HDMI_SPDIF_BASE(0x004C) |
| 475 #define S5P_SPDIFIN_Pc_INFO_1 S5P_HDMI_SPDIF_BASE(0x0050) |
| 476 #define S5P_SPDIFIN_Pc_INFO_2 S5P_HDMI_SPDIF_BASE(0x0054) |
| 477 #define S5P_SPDIFIN_Pd_INFO_1 S5P_HDMI_SPDIF_BASE(0x0058) |
| 478 #define S5P_SPDIFIN_Pd_INFO_2 S5P_HDMI_SPDIF_BASE(0x005C) |
| 479 #define S5P_SPDIFIN_DATA_BUF_0_1 S5P_HDMI_SPDIF_BASE(0x0060) |
| 480 #define S5P_SPDIFIN_DATA_BUF_0_2 S5P_HDMI_SPDIF_BASE(0x0064) |
| 481 #define S5P_SPDIFIN_DATA_BUF_0_3 S5P_HDMI_SPDIF_BASE(0x0068) |
| 482 #define S5P_SPDIFIN_USER_BUF_0 S5P_HDMI_SPDIF_BASE(0x006C) |
| 483 #define S5P_SPDIFIN_DATA_BUF_1_1 S5P_HDMI_SPDIF_BASE(0x0070) |
| 484 #define S5P_SPDIFIN_DATA_BUF_1_2 S5P_HDMI_SPDIF_BASE(0x0074) |
| 485 #define S5P_SPDIFIN_DATA_BUF_1_3 S5P_HDMI_SPDIF_BASE(0x0078) |
| 486 #define S5P_SPDIFIN_USER_BUF_1 S5P_HDMI_SPDIF_BASE(0x007C) |
| 487 |
| 488 #define BLUE_SCR_EN (1<<5) |
| 489 #define BLUE_SCR_DIS (0<<5) |
| 490 #define ASP_EN (1<<2) |
| 491 #define ASP_DIS (0<<2) |
| 492 #define PWDN_ENB_NORMAL (1<<1) |
| 493 #define PWDN_ENB_PD (0<<1) |
| 494 #define HDMI_EN (1<<0) |
| 495 #define HDMI_DIS (~HDMI_EN) |
| 496 |
| 497 #define PX_LMT_CTRL_BYPASS (0<<5) |
| 498 #define PX_LMT_CTRL_RGB (1<<5) |
| 499 #define PX_LMT_CTRL_YPBPR (2<<5) |
| 500 #define PX_LMT_CTRL_RESERVED (3<<5) |
| 501 |
| 502 #define VID_PREAMBLE_EN (0<<5) |
| 503 #define VID_PREAMBLE_DIS (1<<5) |
| 504 #define GUARD_BAND_EN (0<<1) |
| 505 #define GUARD_BAND_DIS (1<<1) |
| 506 |
| 507 #define AUTHEN_ACK_AUTH (1<<7) |
| 508 #define AUTHEN_ACK_NOT (0<<7) |
| 509 #define AUD_FIFO_OVF_FULL (1<<6) |
| 510 #define AUD_FIFO_OVF_NOT (0<<6) |
| 511 #define UPDATE_RI_INT_OCC (1<<4) |
| 512 #define UPDATE_RI_INT_NOT (0<<4) |
| 513 #define UPDATE_RI_INT_CLEAR (1<<4) |
| 514 #define UPDATE_PJ_INT_OCC (1<<3) |
| 515 #define UPDATE_PJ_INT_NOT (0<<3) |
| 516 #define UPDATE_PJ_INT_CLEAR (1<<3) |
| 517 #define EXCHANGEKSV_INT_OCC (1<<2) |
| 518 #define EXCHANGEKSV_INT_NOT (0<<2) |
| 519 #define EXCHANGEKSV_INT_CLEAR (1<<2) |
| 520 #define WATCHDOG_INT_OCC (1<<1) |
| 521 #define WATCHDOG_INT_NOT (0<<1) |
| 522 #define WATCHDOG_INT_CLEAR (1<<1) |
| 523 #define WTFORACTIVERX_INT_OCC (1) |
| 524 #define WTFORACTIVERX_INT_NOT (0) |
| 525 #define WTFORACTIVERX_INT_CLEAR (1) |
| 526 |
| 527 #define AUD_FIFO_OVF_EN (1<<6) |
| 528 #define AUD_FIFO_OVF_DIS (0<<6) |
| 529 #define UPDATE_RI_INT_EN (1<<4) |
| 530 #define UPDATE_RI_INT_DIS (0<<4) |
| 531 #define UPDATE_PJ_INT_EN (1<<3) |
| 532 #define UPDATE_PJ_INT_DIS (0<<3) |
| 533 #define EXCHANGEKSV_INT_EN (1<<2) |
| 534 #define EXCHANGEKSV_INT_DIS (0<<2) |
| 535 #define WATCHDOG_INT_EN (1<<1) |
| 536 #define WATCHDOG_INT_DIS (0<<1) |
| 537 #define WTFORACTIVERX_INT_EN (1) |
| 538 #define WTFORACTIVERX_INT_DIS (0) |
| 539 #define HDCP_STATUS_EN_ALL (UPDATE_RI_INT_EN|\ |
| 540 UPDATE_PJ_INT_DIS|\ |
| 541 EXCHANGEKSV_INT_EN|\ |
| 542 WATCHDOG_INT_EN|\ |
| 543 WTFORACTIVERX_INT_EN) |
| 544 |
| 545 #define HDCP_STATUS_DIS_ALL (~0x1f) |
| 546 |
| 547 #define SW_HPD_PLUGGED (1<<1) |
| 548 #define SW_HPD_UNPLUGGED (0<<1) |
| 549 |
| 550 #define HDMI_MODE_EN (1<<1) |
| 551 #define HDMI_MODE_DIS (0<<1) |
| 552 #define DVI_MODE_EN (1) |
| 553 #define DVI_MODE_DIS (0) |
| 554 |
| 555 #define HDCP_ENC_ENABLE (1) |
| 556 #define HDCP_ENC_DISABLE (0) |
| 557 |
| 558 #define SET_BLUESCREEN_0(x) (0xff&(x)) |
| 559 #define SET_BLUESCREEN_1(x) (0xff&(x)) |
| 560 #define SET_BLUESCREEN_2(x) (0xff&(x)) |
| 561 |
| 562 #define SET_HDMI_YMAX(x) (0xff&(x)) |
| 563 #define SET_HDMI_YMIN(x) (0xff&(x)) |
| 564 #define SET_HDMI_CMAX(x) (0xff&(x)) |
| 565 #define SET_HDMI_CMIN(x) (0xff&(x)) |
| 566 |
| 567 #define SET_VBI_ST_MG(x) (0xff&(x)) |
| 568 #define SET_VBI_END_MG(x) (0xff&(x)) |
| 569 #define SET_VACT_ST_MG(x) (0xff&(x)) |
| 570 |
| 571 #define SET_H_BLANK_L(x) (0xff&(x)) |
| 572 #define SET_H_BLANK_H(x) (0x7&((x)>>8)) |
| 573 #define SET_V2_BLANK_L(x) (0xff&(x)) |
| 574 #define SET_V1_BLANK_L(x) ((0x1f&(x))<<3) |
| 575 #define SET_V2_BLANK_H(x) (0x7&((x)>>8)) |
| 576 #define SET_V1_BLANK_H(x) (0x3f&((x)>>5)) |
| 577 #define SET_V_LINE_L(x) (0xff&(x)) |
| 578 #define SET_H_LINE_L(x) ((0xf&(x))<<4) |
| 579 #define SET_V_LINE_H(x) (0xf&((x)>>8)) |
| 580 #define SET_H_LINE_H(x) (0xff&((x)>>4)) |
| 581 |
| 582 #define V_SYNC_POL_ACT_LOW (1) |
| 583 #define V_SYNC_POL_ACT_HIGH (0) |
| 584 |
| 585 #define INT_PRO_MODE_INTERLACE (1) |
| 586 #define INT_PRO_MODE_PROGRESSIVE (0) |
| 587 |
| 588 #define SET_V_BOT_ST_L(x) (0xff&(x)) |
| 589 #define SET_V_BOT_END_L(x) ((0x1f&(x))<<3) |
| 590 #define SET_V_BOT_ST_H(x) (0x7&((x)>>8)) |
| 591 #define SET_V_BOT_END_H(x) (0x3f&((x)>>5)) |
| 592 |
| 593 #define SET_HSYNC_START_L(x) (0xff&(x)) |
| 594 #define SET_HSYNC_END_L(x) ((0x3f&(x))<<2) |
| 595 #define SET_HSYNC_START_H(x) (0x3&((x)>>8)) |
| 596 |
| 597 #define SET_HSYNC_POL_ACT_LOW (1<<4) |
| 598 #define SET_HSYNC_POL_ACT_HIGH (0<<4) |
| 599 #define SET_HSYNC_END_H(x) (0xf&((x)>>6)) |
| 600 |
| 601 #define SET_VSYNC_T_END_L(x) (0xff&(x)) |
| 602 #define SET_VSYNC_T_ST_L(x) ((0xf&(x))<<4) |
| 603 #define SET_VSYNC_T_END_H(x) (0xf&((x)>>8)) |
| 604 #define SET_VSYNC_T_ST_H(x) (0xff&((x)>>4)) |
| 605 |
| 606 #define SET_VSYNC_B_END_L(x) (0xff&(x)) |
| 607 #define SET_VSYNC_B_ST_L(x) ((0xf&(x))<<4) |
| 608 #define SET_VSYNC_B_END_H(x) (0xf&((x)>>8)) |
| 609 #define SET_VSYNC_B_ST_H(x) (0xff&((x)>>4)) |
| 610 |
| 611 #define SET_VSYNC_H_POST_END_L(x) (0xff&(x)) |
| 612 #define SET_VSYNC_H_POST_ST_L(x) ((0xf&(x))<<4) |
| 613 #define SET_VSYNC_H_POST_END_H(x) (0xf&((x)>>8)) |
| 614 #define SET_VSYNC_H_POST_ST_H(x) (0xff&((x)>>4)) |
| 615 |
| 616 #define SACD_EN (1<<5) |
| 617 #define SACD_DIS (0<<5) |
| 618 #define AUD_MODE_MULTI_CH (1<<4) |
| 619 #define AUD_MODE_2_CH (0<<4) |
| 620 #define SET_SP_PRE(x) (0xf&(x)) |
| 621 |
| 622 #define SET_SP_FLAT(x) (0xf&(x)) |
| 623 |
| 624 #define SPK3R_SEL_I_PCM0L (0<<27) |
| 625 #define SPK3R_SEL_I_PCM0R (1<<27) |
| 626 #define SPK3R_SEL_I_PCM1L (2<<27) |
| 627 #define SPK3R_SEL_I_PCM1R (3<<27) |
| 628 #define SPK3R_SEL_I_PCM2L (4<<27) |
| 629 #define SPK3R_SEL_I_PCM2R (5<<27) |
| 630 #define SPK3R_SEL_I_PCM3L (6<<27) |
| 631 #define SPK3R_SEL_I_PCM3R (7<<27) |
| 632 #define SPK3L_SEL_I_PCM0L (0<<24) |
| 633 #define SPK3L_SEL_I_PCM0R (1<<24) |
| 634 #define SPK3L_SEL_I_PCM1L (2<<24) |
| 635 #define SPK3L_SEL_I_PCM1R (3<<24) |
| 636 #define SPK3L_SEL_I_PCM2L (4<<24) |
| 637 #define SPK3L_SEL_I_PCM2R (5<<24) |
| 638 #define SPK3L_SEL_I_PCM3L (6<<24) |
| 639 #define SPK3L_SEL_I_PCM3R (7<<24) |
| 640 #define SPK2R_SEL_I_PCM0L (0<<19) |
| 641 #define SPK2R_SEL_I_PCM0R (1<<19) |
| 642 #define SPK2R_SEL_I_PCM1L (2<<19) |
| 643 #define SPK2R_SEL_I_PCM1R (3<<19) |
| 644 #define SPK2R_SEL_I_PCM2L (4<<19) |
| 645 #define SPK2R_SEL_I_PCM2R (5<<19) |
| 646 #define SPK2R_SEL_I_PCM3L (6<<19) |
| 647 #define SPK2R_SEL_I_PCM3R (7<<19) |
| 648 #define SPK2L_SEL_I_PCM0L (0<<16) |
| 649 #define SPK2L_SEL_I_PCM0R (1<<16) |
| 650 #define SPK2L_SEL_I_PCM1L (2<<16) |
| 651 #define SPK2L_SEL_I_PCM1R (3<<16) |
| 652 #define SPK2L_SEL_I_PCM2L (4<<16) |
| 653 #define SPK2L_SEL_I_PCM2R (5<<16) |
| 654 #define SPK2L_SEL_I_PCM3L (6<<16) |
| 655 #define SPK2L_SEL_I_PCM3R (7<<16) |
| 656 #define SPK1R_SEL_I_PCM0L (0<<11) |
| 657 #define SPK1R_SEL_I_PCM0R (1<<11) |
| 658 #define SPK1R_SEL_I_PCM1L (2<<11) |
| 659 #define SPK1R_SEL_I_PCM1R (3<<11) |
| 660 #define SPK1R_SEL_I_PCM2L (4<<11) |
| 661 #define SPK1R_SEL_I_PCM2R (5<<11) |
| 662 #define SPK1R_SEL_I_PCM3L (6<<11) |
| 663 #define SPK1R_SEL_I_PCM3R (7<<11) |
| 664 #define SPK1L_SEL_I_PCM0L (0<<8) |
| 665 #define SPK1L_SEL_I_PCM0R (1<<8) |
| 666 #define SPK1L_SEL_I_PCM1L (2<<8) |
| 667 #define SPK1L_SEL_I_PCM1R (3<<8) |
| 668 #define SPK1L_SEL_I_PCM2L (4<<8) |
| 669 #define SPK1L_SEL_I_PCM2R (5<<8) |
| 670 #define SPK1L_SEL_I_PCM3L (6<<8) |
| 671 #define SPK1L_SEL_I_PCM3R (7<<8) |
| 672 #define SPK0R_SEL_I_PCM0L (0<<3) |
| 673 #define SPK0R_SEL_I_PCM0R (1<<3) |
| 674 #define SPK0R_SEL_I_PCM1L (2<<3) |
| 675 #define SPK0R_SEL_I_PCM1R (3<<3) |
| 676 #define SPK0R_SEL_I_PCM2L (4<<3) |
| 677 #define SPK0R_SEL_I_PCM2R (5<<3) |
| 678 #define SPK0R_SEL_I_PCM3L (6<<3) |
| 679 #define SPK0R_SEL_I_PCM3R (7<<3) |
| 680 #define SPK0L_SEL_I_PCM0L (0) |
| 681 #define SPK0L_SEL_I_PCM0R (1) |
| 682 #define SPK0L_SEL_I_PCM1L (2) |
| 683 #define SPK0L_SEL_I_PCM1R (3) |
| 684 #define SPK0L_SEL_I_PCM2L (4) |
| 685 #define SPK0L_SEL_I_PCM2R (5) |
| 686 #define SPK0L_SEL_I_PCM3L (6) |
| 687 #define SPK0L_SEL_I_PCM3R (7) |
| 688 |
| 689 #define ALT_CTS_RATE_CTS_1 (0<<3) |
| 690 #define ALT_CTS_RATE_CTS_11 (1<<3) |
| 691 #define ALT_CTS_RATE_CTS_21 (2<<3) |
| 692 #define ALT_CTS_RATE_CTS_31 (3<<3) |
| 693 #define ACR_TX_MODE_NO_TX (0) |
| 694 #define ACR_TX_MODE_TX_ONCE (1) |
| 695 #define ACR_TX_MODE_TXCNT_VBI (2) |
| 696 #define ACR_TX_MODE_TX_VPC (3) |
| 697 #define ACR_TX_MODE_MESURE_CTS (4) |
| 698 |
| 699 #define SET_ACR_MCTS(x) (0xfffff&(x)) |
| 700 #define SET_ACR_CTS(x) (0xfffff&(x)) |
| 701 #define SET_ACR_N(x) (0xfffff&(x)) |
| 702 #define SET_ACR_LSB2(x) (0xff&(x)) |
| 703 #define SET_ACR_TXCNT(x) (0x1f&(x)) |
| 704 #define SET_ACR_TX_INTERNAL(x) (0xff&(x)) |
| 705 #define SET_ACR_CTS_OFFSET(x) (0xff&(x)) |
| 706 |
| 707 #define GCP_CON_NO_TRAN (0) |
| 708 #define GCP_CON_TRANS_ONCE (1) |
| 709 #define GCP_CON_TRANS_EVERY_VSYNC (2) |
| 710 |
| 711 #define SET_GCP_BYTE1(x) (0xff&(x)) |
| 712 |
| 713 #define SET_ACP_FR_RATE(x) ((0x1f&(x))<<3) |
| 714 #define ACP_CON_NO_TRAN (0) |
| 715 #define ACP_CON_TRANS_ONCE (1) |
| 716 #define ACP_CON_TRANS_EVERY_VSYNC (2) |
| 717 |
| 718 #define SET_ACP_TYPE(x) (0xff&(x)) |
| 719 #define SET_ACP_DATA(x) (0xff&(x)) |
| 720 |
| 721 #define SET_ISRC_FR_RATE(x) ((0x1f&(x))<<3) |
| 722 #define ISRC_EN (1<<2) |
| 723 #define ISRC_DIS (0<<2) |
| 724 #define ISRC_TX_CON_NO_TRANS (0) |
| 725 #define ISRC_TX_CON_TRANS_ONCE (1) |
| 726 #define ISRC_TX_CON_TRANS_EVERY_VSYNC (2) |
| 727 |
| 728 #define SET_ISRC1_HEADER(x) (0xff&(x)) |
| 729 #define SET_ISRC1_DATA(x) (0xff&(x)) |
| 730 #define SET_ISRC2_DATA(x) (0xff&(x)) |
| 731 |
| 732 #define AVI_TX_CON_NO_TRANS (0) |
| 733 #define AVI_TX_CON_TRANS_ONCE (1) |
| 734 #define AVI_TX_CON_TRANS_EVERY_VSYNC (2) |
| 735 |
| 736 #define SET_AVI_CHECK_SUM(x) (0xff&(x)) |
| 737 |
| 738 #define HDMI_CON_PXL_REP_RATIO_MASK (1<<1 | 1<<0) |
| 739 #define HDMI_DOUBLE_PIXEL_REPETITION (0x01) |
| 740 #define AVI_PIXEL_REPETITION_DOUBLE (1<<0) |
| 741 #define AVI_PICTURE_ASPECT_4_3 (1<<4) |
| 742 #define AVI_PICTURE_ASPECT_16_9 (1<<5) |
| 743 |
| 744 #define SET_AVI_BYTE(x) (0xff&(x)) |
| 745 |
| 746 #define AUI_TX_CON_NO_TRANS (0) |
| 747 #define AUI_TX_CON_TRANS_ONCE (1) |
| 748 #define AUI_TX_CON_TRANS_EVERY_VSYNC (2) |
| 749 |
| 750 #define SET_AUI_CHECK_SUM(x) (0xff&(x)) |
| 751 #define SET_AUI_BYTE(x) (0xff&(x)) |
| 752 |
| 753 #define MPG_TX_CON_NO_TRANS (0) |
| 754 #define MPG_TX_CON_TRANS_ONCE (1) |
| 755 #define MPG_TX_CON_TRANS_EVERY_VSYNC (2) |
| 756 |
| 757 #define SET_MPG_CHECK_SUM(x) (0xff&(x)) |
| 758 #define SET_MPG_BYTE(x) (0xff&(x)) |
| 759 |
| 760 #define SPD_TX_CON_NO_TRANS (0) |
| 761 #define SPD_TX_CON_TRANS_ONCE (1) |
| 762 #define SPD_TX_CON_TRANS_EVERY_VSYNC (2) |
| 763 |
| 764 #define SET_SPD_HEADER(x) (0xff&(x)) |
| 765 #define SET_SPD_DATA(x) (0xff&(x)) |
| 766 |
| 767 #define OUT_OFFSET_SEL_RGB_FR (0<<4) |
| 768 #define OUT_OFFSET_SEL_RGB_LR (2<<4) |
| 769 #define OUT_OFFSET_SEL_YCBCR (3<<4) |
| 770 #define IN_CLIP_EN (1<<2) |
| 771 #define IN_CLIP_DIS (0<<2) |
| 772 #define IN_OFFSET_SEL_RGB_FR (0) |
| 773 #define IN_OFFSET_SEL_RGB_LR (2) |
| 774 #define IN_OFFSET_SEL_YCBCR (3) |
| 775 |
| 776 #define SET_HDMI_CSC_COEF_L(x) (0xff&(x)) |
| 777 #define SET_HDMI_CSC_COEF_H(x) (0x3&((x)>>8)) |
| 778 |
| 779 #define SET_HDMI_SHA1(x) (0xff&(x)) |
| 780 |
| 781 #define GETSYNC_TYPE_EN (1<<4) |
| 782 #define GETSYNC_TYPE_DIS (~GETSYNC_TYPE_EN) |
| 783 #define GETSYNC_EN (1<<3) |
| 784 #define GETSYNC_DIS (~GETSYNC_EN) |
| 785 #define FIELD_EN (1<<1) |
| 786 #define FIELD_DIS (~FIELD_EN) |
| 787 #define TG_EN (1) |
| 788 #define TG_DIS (~TG_EN) |
| 789 |
| 790 #define SET_TG_H_FSZ_L(x) (0xff&(x)) |
| 791 #define SET_TG_H_FSZ_H(x) (0x1f&((x)>>8)) |
| 792 #define SET_TG_HACT_ST_L(x) (0xff&(x)) |
| 793 #define SET_TG_HACT_ST_H(x) (0xf&((x)>>8)) |
| 794 #define SET_TG_HACT_SZ_L(x) (0xff&(x)) |
| 795 #define SET_TG_HACT_SZ_H(x) (0xf&((x)>>8)) |
| 796 #define SET_TG_V_FSZ_L(x) (0xff&(x)) |
| 797 #define SET_TG_V_FSZ_H(x) (0x7&((x)>>8)) |
| 798 #define SET_TG_VSYNC_L(x) (0xff&(x)) |
| 799 #define SET_TG_VSYNC_H(x) (0x7&((x)>>8)) |
| 800 #define SET_TG_VSYNC2_L(x) (0xff&(x)) |
| 801 #define SET_TG_VSYNC2_H(x) (0x7&((x)>>8)) |
| 802 #define SET_TG_VACT_ST_L(x) (0xff&(x)) |
| 803 #define SET_TG_VACT_ST_H(x) (0x7&((x)>>8)) |
| 804 #define SET_TG_VACT_SZ_L(x) (0xff&(x)) |
| 805 #define SET_TG_VACT_SZ_H(x) (0x7&((x)>>8)) |
| 806 #define SET_TG_FIELD_CHG_L(x) (0xff&(x)) |
| 807 #define SET_TG_FIELD_CHG_H(x) (0x7&((x)>>8)) |
| 808 #define SET_TG_VACT_ST2_L(x) (0xff&(x)) |
| 809 #define SET_TG_VACT_ST2_H(x) (0x7&((x)>>8)) |
| 810 |
| 811 #define SET_TG_VSYNC_TOP_HDMI_L(x) (0xff&(x)) |
| 812 #define SET_TG_VSYNC_TOP_HDMI_H(x) (0x7&((x)>>8)) |
| 813 #define SET_TG_VSYNC_BOT_HDMI_L(x) (0xff&(x)) |
| 814 #define SET_TG_VSYNC_BOT_HDMI_H(x) (0x7&((x)>>8)) |
| 815 #define SET_TG_FIELD_TOP_HDMI_L(x) (0xff&(x)) |
| 816 #define SET_TG_FIELD_TOP_HDMI_H(x) (0x7&((x)>>8)) |
| 817 #define SET_TG_FIELD_BOT_HDMI_L(x) (0xff&(x)) |
| 818 #define SET_TG_FIELD_BOT_HDMI_H(x) (0x7&((x)>>8)) |
| 819 |
| 820 #define IRQ_WRONG_SIGNAL_ENABLE (1<<0) |
| 821 #define IRQ_CH_STATUS_RECOVERED_ENABLE (1<<1) |
| 822 #define IRQ_WRONG_PREAMBLE_ENABLE (1<<2) |
| 823 #define IRQ_STREAM_HEADER_NOT_DETECTED_ENABLE (1<<3) |
| 824 #define IRQ_STREAM_HEADER_DETECTED_ENABLE (1<<4) |
| 825 #define IRQ_STREAM_HEADER_NOT_DETECTED_AT_RIGHTTIME_ENABLE (1<<5) |
| 826 #define IRQ_ABNORMAL_PD_ENABLE (1<<6) |
| 827 #define IRQ_BUFFER_OVERFLOW_ENABLE (1<<7) |
| 828 |
| 829 #define CONFIG_FILTER_3_SAMPLE (0<<6) |
| 830 #define CONFIG_FILTER_2_SAMPLE (1<<6) |
| 831 #define CONFIG_LINEAR_PCM_TYPE (0<<5) |
| 832 #define CONFIG_NON_LINEAR_PCM_TYPE (1<<5) |
| 833 #define CONFIG_PCPD_AUTO_SET (0<<4) |
| 834 #define CONFIG_PCPD_MANUAL_SET (1<<4) |
| 835 #define CONFIG_WORD_LENGTH_AUTO_SET (0<<3) |
| 836 #define CONFIG_WORD_LENGTH_MANUAL_SET (1<<3) |
| 837 #define CONFIG_U_V_C_P_NEGLECT (0<<2) |
| 838 #define CONFIG_U_V_C_P_REPORT (1<<2) |
| 839 #define CONFIG_BURST_SIZE_1 (0<<1) |
| 840 #define CONFIG_BURST_SIZE_2 (1<<1) |
| 841 #define CONFIG_DATA_ALIGN_16BIT (0<<0) |
| 842 #define CONFIG_DATA_ALIGN_32BIT (1<<0) |
| 843 |
| 844 #define AUTHEN_ACK_POS 7 |
| 845 #define AUD_FIFO_OVF_POS 6 |
| 846 |
| 847 #define UPDATE_RI_INT_POS 4 |
| 848 #define UPDATE_PJ_INT_POS 3 |
| 849 #define EXCHANGEKSV_INT_POS 2 |
| 850 #define WATCHDOG_INT_POS 1 |
| 851 #define WTFORACTIVERX_INT_POS 0 |
| 852 |
| 853 #define AUTHENTICATED (0x1 << 7) |
| 854 #define NOT_YET_AUTHENTICATED (0x0 << 7) |
| 855 #define AUD_FIFO_OVF_INT_OCCURRED (0x1 << 6) |
| 856 #define AUD_FIFO_OVF_INT_NOT_OCCURRED (0x0 << 6) |
| 857 |
| 858 #define UPDATE_RI_INT_OCCURRED (0x1 << 4) |
| 859 #define UPDATE_RI_INT_NOT_OCCURRED (0x0 << 4) |
| 860 #define UPDATE_PJ_INT_OCCURRED (0x1 << 3) |
| 861 #define UPDATE_PJ_INT_NOT_OCCURRED (0x0 << 3) |
| 862 #define EXCHANGEKSV_INT_OCCURRED (0x1 << 2) |
| 863 #define EXCHANGEKSV_INT_NOT_OCCURRED (0x0 << 2) |
| 864 #define WATCHDOG_INT_OCCURRED (0x1 << 1) |
| 865 #define WATCHDOG_INT_NOT_OCCURRED (0x0 << 1) |
| 866 #define WTFORACTIVERX_INT_OCCURRED (0x1 << 0) |
| 867 #define WTFORACTIVERX_INT_NOT_OCCURRED (0x0 << 0) |
| 868 |
| 869 #define AUD_FIFO_OVF_INT_EN (0x1 << 6) |
| 870 #define AUD_FIFO_OVF_INT_DIS (0x0 << 6) |
| 871 |
| 872 #define EFUSE_CTRL_ACTIVATE (1) |
| 873 #define EFUSE_ADDR_WIDTH (240) |
| 874 #define EFUSE_SIGDEV_ASSERT (0) |
| 875 #define EFUSE_SIGDEV_DEASSERT (96) |
| 876 #define EFUSE_PRCHG_ASSERT (0) |
| 877 #define EFUSE_PRCHG_DEASSERT (144) |
| 878 #define EFUSE_FSET_ASSERT (48) |
| 879 #define EFUSE_FSET_DEASSERT (192) |
| 880 #define EFUSE_SENSING (240) |
| 881 #define EFUSE_SCK_ASSERT (48) |
| 882 #define EFUSE_SCK_DEASSERT (144) |
| 883 #define EFUSE_SDOUT_OFFSET (192) |
| 884 #define EFUSE_READ_OFFSET (192) |
| 885 |
| 886 #define EFUSE_ECC_DONE (1<<0) |
| 887 #define EFUSE_ECC_BUSY (1<<1) |
| 888 #define EFUSE_ECC_FAIL (1<<2) |
| 889 |
| 890 #define EN_PJ_EN (0x1 << 4) |
| 891 #define EN_PJ_DIS (~EN_PJ_EN) |
| 892 |
| 893 #define SET_REPEATER_TIMEOUT (0x1 << 2) |
| 894 #define CLEAR_REPEATER_TIMEOUT (~SET_REPEATER_TIMEOUT) |
| 895 #define CP_DESIRED_EN (0x1 << 1) |
| 896 #define CP_DESIRED_DIS (~CP_DESIRED_EN) |
| 897 #define ENABLE_1_DOT_1_FEATURE_EN (0x1 << 0) |
| 898 #define ENABLE_1_DOT_1_FEATURE_DIS (~ENABLE_1_DOT_1_FEATURE_EN) |
| 899 |
| 900 #define Pi_MATCH_RESULT__YES ((0x1<<3) | (0x1<<2)) |
| 901 #define Pi_MATCH_RESULT__NO ((0x1<<3) | (0x0<<2)) |
| 902 #define Ri_MATCH_RESULT__YES ((0x1<<1) | (0x1<<0)) |
| 903 #define Ri_MATCH_RESULT__NO ((0x1<<1) | (0x0<<0)) |
| 904 #define CLEAR_ALL_RESULTS 0x0 |
| 905 |
| 906 #define HDCP_ENC_DIS (0x0 << 0) |
| 907 |
| 908 #define REPEATER_SET (0x1 << 6) |
| 909 #define REPEATERP_CLEAR (0x1 << 6) |
| 910 #define READY_SET (0x1 << 5) |
| 911 #define READY_CLEAR (0x1 << 5) |
| 912 #define FAST_SET (0x1 << 4) |
| 913 #define FAST_CLEAR (0x1 << 4) |
| 914 #define ONE_DOT_ONE_FEATURES_SET (0x1 << 1) |
| 915 #define ONE_DOT_ONE_FEATURES_CLEAR (0x1 << 1) |
| 916 #define FAST_REAUTHENTICATION_SET (0x1 << 0) |
| 917 #define FAST_REAUTHENTICATION_CLEAR (0x1 << 0) |
| 918 |
| 919 #define SCRAMBLER_KEY_START_EN (0x1 << 7) |
| 920 #define SCRAMBLER_KEY_START_DIS (~SCRAMBLER_KEY_START_EN) |
| 921 #define SCRAMBLER_KEY_DONE (0x1 << 6) |
| 922 #define SCRAMBLER_KEY_GENERATING (0x0 << 6) |
| 923 |
| 924 #define HAES_START_EN (0x1 << 0) |
| 925 #define HAES_DECRYPTION_DONE (0x0 << 0) |
| 926 |
| 927 #define AN_SIZE 8 |
| 928 #define AKSV_SIZE 5 |
| 929 #define BKSV_SIZE 5 |
| 930 #define HDCPLink_Addr 0x74 |
| 931 |
| 932 #define CABLE_PLUGGED (1<<1) |
| 933 #define CABLE_UNPLUGGED (0<<1) |
| 934 |
| 935 #define DDC_Addr 0xA0 |
| 936 #define eDDC_Addr 0x60 |
| 937 #define HDCPLink_Addr 0x74 |
| 938 |
| 939 #define HDCP_Bksv 0x00 |
| 940 #define HDCP_Aksv 0x10 |
| 941 #define HDCP_Ainfo 0x15 |
| 942 #define HDCP_An 0x18 |
| 943 #define HDCP_Ri 0x08 |
| 944 #define HDCP_Bcaps 0x40 |
| 945 #define HDCP_BStatus 0x41 |
| 946 #define HDCP_Pj 0x0a |
| 947 |
| 948 #define HDCP_KSVFIFO 0x43 |
| 949 #define HDCP_SHA1 0x20 |
| 950 |
| 951 #define HDMI_MODE_HDMI 0 |
| 952 #define HDMI_MODE_DVI 1 |
| 953 |
| 954 #define EDID_SEGMENT_ID 0x60 |
| 955 #define EDID_SEGMENT0 0x00 |
| 956 #define EDID_SEGMENT1 0x01 |
| 957 |
| 958 #define EDID_DEVICE_ID 0xA0 |
| 959 #define EDID_ADDR_START 0x00 |
| 960 #define EDID_ADDR_EXT 0x80 |
| 961 #define EDID_RCOUNT 127 |
| 962 |
| 963 #define EDID_POS_EXTENSION 0x7E |
| 964 #define EDID_POS_CHECKSUM 0x7F |
| 965 #define VALID_EDID 0xA5 |
| 966 #define NO_VALID_EDID 0 |
| 967 |
| 968 #define EDID_POS_RBUFFER0 0x00 |
| 969 #define EDID_POS_RBUFFER1 0x80 |
| 970 #define EDID_POS_RBUFFER2 0x100 |
| 971 #define EDID_POS_RBUFFER3 0x180 |
| 972 |
| 973 #define EDID_TIMING_EXT_TAG_ADDR_POS 0x80 |
| 974 #define EDID_TIMING_EXT_REV_NUMBER 0x81 |
| 975 #define EDID_DETAILED_TIMING_OFFSET_POS 0x82 |
| 976 #define EDID_COLOR_SPACE_ADDR 0x83 |
| 977 #define EDID_DATA_BLOCK_ADDRESS 0x84 |
| 978 #define EDID_TIMING_EXT_TAG_VAL 0x02 |
| 979 #define EDID_YCBCR444_CS_MASK 0x20 |
| 980 #define EDID_YCBCR422_CS_MASK 0x10 |
| 981 #define EDID_TAG_CODE_MASK 0xE0 |
| 982 #define EDID_DATA_BLOCK_SIZE_MASK 0x1F |
| 983 #define EDID_NATIVE_RESOLUTION_MASK 0x80 |
| 984 |
| 985 #define EDID_SHORT_AUD_DEC_TAG 0x20 |
| 986 #define EDID_SHORT_VID_DEC_TAG 0x40 |
| 987 #define EDID_HDMI_VSDB_TAG 0x60 |
| 988 #define EDID_SPEAKER_ALLOCATION_TAG 0x80 |
| 989 |
| 990 #define COLOR_SPACE_RGB 0 |
| 991 #define COLOR_SPACE_YCBCR444 1 |
| 992 #define COLOR_SPACE_YCBCR422 2 |
| 993 |
| 994 #define SHORT_VID_720_480P_4_3_NT 0x01 |
| 995 #define SHORT_VID_720_480P_16_9_NT 0x02 |
| 996 #define SHORT_VID_1280_720P_16_9_NT 0x04 |
| 997 #define SHORT_VID_1920_1080i_16_9_NT 0x08 |
| 998 #define SHORT_VID_720_576P_4_3_PAL 0x10 |
| 999 #define SHORT_VID_720_576P_16_9_PAL 0x20 |
| 1000 #define SHORT_VID_1280_720P_16_9_PAL 0x40 |
| 1001 #define SHORT_VID_1920_1080i_16_9_PAL 0x80 |
| 1002 |
| 1003 #define SET_HDMI_RESOLUTION_480P 0x00 |
| 1004 #define SET_HDMI_RESOLUTION_720P 0x01 |
| 1005 #define SET_HDMI_RESOLUTION_1080i 0x02 |
| 1006 |
| 1007 #define HDMI_WAIT_TIMEOUT 20 |
| 1008 #define AUTHENTICATION_SUCCESS 0 |
| 1009 #define AUTHENTICATION_FAILURE 1 |
| 1010 #define AUTHENTICATION_FAIL_CNT 2 |
| 1011 |
| 1012 #define HDCP_MAX_DEVS 128 |
| 1013 #define HDCP_KSV_SIZE 5 |
| 1014 |
| 1015 #define CMD_IIC_ADDRMODE_CHANGE 0xFF |
| 1016 |
| 1017 /* IIC Addressing Mode Definition */ |
| 1018 #define IIC_ADDRMODE_1 0 |
| 1019 #define IIC_ADDRMODE_2 1 |
| 1020 #define IIC_ADDRMODE_3 2 |
| 1021 #define HDMI_IIC_ADDRMODE IIC_ADDRMODE_1 |
| 1022 |
| 1023 #define IIC_ACK 0 |
| 1024 #define IIC_NOACK 1 |
| 1025 |
| 1026 #define EDID_POS_ERROR 512 |
| 1027 #define R_VAL_RETRY_CNT 5 |
| 1028 |
| 1029 #define CABLE_INSERT 1 |
| 1030 #define CABLE_REMOVE (~CABLE_INSERT) |
| 1031 |
| 1032 #define HDMI_PHY_READY (1<<0) |
| 1033 |
| 1034 /* |
| 1035 * Color Depth |
| 1036 * CD0, CD1, CD2, CD3 |
| 1037 */ |
| 1038 |
| 1039 #define GCP_CD_NOT_INDICATED 0 |
| 1040 #define GCP_CD_24BPP (1<<2) |
| 1041 #define GCP_CD_30BPP (1<<0 | 1<<2) |
| 1042 #define GCP_CD_36BPP (1<<1 | 1<<2) |
| 1043 #define GCP_CD_48BPP (1<<0 | 1<<1 | 1<<2) |
| 1044 |
| 1045 #define GCP_DEFAULT_PHASE 1 |
| 1046 |
| 1047 /* for DC_CONTRAL */ |
| 1048 #define HDMI_DC_CTL_8 0 |
| 1049 #define HDMI_DC_CTL_10 (1<<0) |
| 1050 #define HDMI_DC_CTL_12 (1<<1) |
| 1051 |
| 1052 #define DO_NOT_TRANSMIT (0) |
| 1053 |
| 1054 #define HPD_SW_ENABLE (1<<0) |
| 1055 #define HPD_SW_DISABLE (0) |
| 1056 #define HPD_ON (1<<1) |
| 1057 #define HPD_OFF (0) |
| 1058 |
| 1059 #define S5P_GPH1_4_HDMI_CEC (0x4 << 16) |
| 1060 #define S5P_GPH1_4_EXT_INT31_4 (0xf << 16) |
| 1061 |
| 1062 #define S5P_GPH1_5_HDMI_HPD (0x4 << 20) |
| 1063 #define S5P_GPH1_5_EXT_INT31_5 (0xf << 20) |
| 1064 |
| 1065 #endif /* __ASM_ARCH_REGS_HDMI_H */ |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 2060003:
ARM: S5PV210: Add TV out driver register definition files (Closed)
Base URL: swsolcc@12.23.106.100:kernel-samsung.git