Fix a couple of typos reported as V8 issue 226.

src/disasm-ia32.cc

 // Copyright 2007-2008 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 682 matching lines @@
     case 0xB7: return "movzx_w";
     case 0xAF: return "imul";
     case 0xA5: return "shld";
     case 0xAD: return "shrd";
     case 0xAB: return "bts";
     default: return NULL;
   }
 }
 
 
-// Disassembled instruction '*instr' and writes it intro 'out_buffer'.
+// Disassembled instruction '*instr' and writes it into 'out_buffer'.
 int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
                                         byte* instr) {
   tmp_buffer_pos_ = 0;  // starting to write as position 0
   byte* data = instr;
   // Check for hints.
   const char* branch_hint = NULL;
-  // We use this two prefixes only with branch prediction
+  // We use these two prefixes only with branch prediction
   if (*data == 0x3E /*ds*/) {
     branch_hint = "predicted taken";
     data++;
   } else if (*data == 0x2E /*cs*/) {
     branch_hint = "predicted not taken";
     data++;
   }
   bool processed = true;  // Will be set to false if the current instruction
                           // is not in 'instructions' table.
   const InstructionDesc& idesc = instruction_table.Get(*data);
@@ skipping 409 matching lines @@
     }
     for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
       fprintf(f, "  ");
     }
     fprintf(f, "  %s\n", buffer.start());
   }
 }
 
 
 }  // namespace disasm