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Issue 2019003: ldrd/strd Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 7 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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721 721
722 722
723 // Get the register from the architecture state. This function does handle 723 // Get the register from the architecture state. This function does handle
724 // the special case of accessing the PC register. 724 // the special case of accessing the PC register.
725 int32_t Simulator::get_register(int reg) const { 725 int32_t Simulator::get_register(int reg) const {
726 ASSERT((reg >= 0) && (reg < num_registers)); 726 ASSERT((reg >= 0) && (reg < num_registers));
727 return registers_[reg] + ((reg == pc) ? Instr::kPCReadOffset : 0); 727 return registers_[reg] + ((reg == pc) ? Instr::kPCReadOffset : 0);
728 } 728 }
729 729
730 730
731 void Simulator::set_dw_register(int dreg, const int* dbl) {
732 ASSERT((dreg >= 0) && (dreg < num_d_registers));
733 registers_[dreg] = dbl[0];
734 registers_[dreg + 1] = dbl[1];
735 }
736
737
731 // Raw access to the PC register. 738 // Raw access to the PC register.
732 void Simulator::set_pc(int32_t value) { 739 void Simulator::set_pc(int32_t value) {
733 pc_modified_ = true; 740 pc_modified_ = true;
734 registers_[pc] = value; 741 registers_[pc] = value;
735 } 742 }
736 743
737 744
738 // Raw access to the PC register without the special adjustment when reading. 745 // Raw access to the PC register without the special adjustment when reading.
739 int32_t Simulator::get_pc() const { 746 int32_t Simulator::get_pc() const {
740 return registers_[pc]; 747 return registers_[pc];
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994 *ptr = value; 1001 *ptr = value;
995 } 1002 }
996 1003
997 1004
998 void Simulator::WriteB(int32_t addr, int8_t value) { 1005 void Simulator::WriteB(int32_t addr, int8_t value) {
999 int8_t* ptr = reinterpret_cast<int8_t*>(addr); 1006 int8_t* ptr = reinterpret_cast<int8_t*>(addr);
1000 *ptr = value; 1007 *ptr = value;
1001 } 1008 }
1002 1009
1003 1010
1011 int32_t* Simulator::ReadDW(int32_t addr) {
1012 #if V8_TARGET_CAN_READ_UNALIGNED
1013 int32_t* ptr = reinterpret_cast<int32_t *>(addr);
Erik Corry 2010/05/07 20:04:34 I removed a space here for you.
1014 return ptr;
1015 #else
1016 if ((addr & 3) == 0) {
1017 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
1018 return *ptr;
Erik Corry 2010/05/07 20:04:34 I don't see how this compiles. It should be retur
1019 }
1020 PrintF("Unaligned read at 0x%08x\n", addr);
1021 UNIMPLEMENTED();
1022 return 0;
1023 #endif
1024 }
1025
1026
1027 void Simulator::WriteDW(int32_t addr, int32_t value1, int32_t value2) {
1028 #if V8_TARGET_CAN_READ_UNALIGNED
1029 int32_t* ptr = reinterpret_cast<int32_t*>(addr);
1030 *ptr++ = value1;
1031 *ptr = value2;
1032 return;
1033 #else
1034 if ((addr & 3) == 0) {
1035 int32_t* ptr = reinterpret_cast<int32_t*>(addr);
1036 *ptr++ = value1;
1037 *ptr = value2;
1038 return;
1039 }
1040 PrintF("Unaligned write at 0x%08x, pc=%p\n", addr, instr);
Erik Corry 2010/05/07 20:04:34 There's no variable called instr here so this does
1041 UNIMPLEMENTED();
1042 #endif
1043 }
1044
1045
1004 // Returns the limit of the stack area to enable checking for stack overflows. 1046 // Returns the limit of the stack area to enable checking for stack overflows.
1005 uintptr_t Simulator::StackLimit() const { 1047 uintptr_t Simulator::StackLimit() const {
1006 // Leave a safety margin of 256 bytes to prevent overrunning the stack when 1048 // Leave a safety margin of 256 bytes to prevent overrunning the stack when
1007 // pushing values. 1049 // pushing values.
1008 return reinterpret_cast<uintptr_t>(stack_) + 256; 1050 return reinterpret_cast<uintptr_t>(stack_) + 256;
1009 } 1051 }
1010 1052
1011 1053
1012 // Unsupported instructions use Format to print an error and stop execution. 1054 // Unsupported instructions use Format to print an error and stop execution.
1013 void Simulator::Format(Instr* instr, const char* format) { 1055 void Simulator::Format(Instr* instr, const char* format) {
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1621 } 1663 }
1622 break; 1664 break;
1623 } 1665 }
1624 default: { 1666 default: {
1625 // The PU field is a 2-bit field. 1667 // The PU field is a 2-bit field.
1626 UNREACHABLE(); 1668 UNREACHABLE();
1627 break; 1669 break;
1628 } 1670 }
1629 } 1671 }
1630 } 1672 }
1631 if (instr->HasH()) { 1673 if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) {
1674 ASSERT((rd % 2) == 0);
1675 if (instr->HasH()) {
1676 // The strd instruction.
1677 int32_t value1 = get_register(rd);
1678 int32_t value2 = get_register(rd+1);
1679 WriteDW(addr, value1, value2);
1680 } else {
1681 // The ldrd instruction.
1682 int* rn_data = ReadDW(addr);
1683 set_dw_register(rd, rn_data);
1684 }
1685 } else if (instr->HasH()) {
1632 if (instr->HasSign()) { 1686 if (instr->HasSign()) {
1633 if (instr->HasL()) { 1687 if (instr->HasL()) {
1634 int16_t val = ReadH(addr, instr); 1688 int16_t val = ReadH(addr, instr);
1635 set_register(rd, val); 1689 set_register(rd, val);
1636 } else { 1690 } else {
1637 int16_t val = get_register(rd); 1691 int16_t val = get_register(rd);
1638 WriteH(addr, val, instr); 1692 WriteH(addr, val, instr);
1639 } 1693 }
1640 } else { 1694 } else {
1641 if (instr->HasL()) { 1695 if (instr->HasL()) {
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2670 int current_sp = get_register(sp); 2724 int current_sp = get_register(sp);
2671 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); 2725 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
2672 uintptr_t address = *stack_slot; 2726 uintptr_t address = *stack_slot;
2673 set_register(sp, current_sp + sizeof(uintptr_t)); 2727 set_register(sp, current_sp + sizeof(uintptr_t));
2674 return address; 2728 return address;
2675 } 2729 }
2676 2730
2677 } } // namespace assembler::arm 2731 } } // namespace assembler::arm
2678 2732
2679 #endif // __arm__ 2733 #endif // __arm__
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