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Side by Side Diff: src/arm/assembler-arm.cc

Issue 2019003: ldrd/strd Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 7 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1150 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) { 1150 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
1151 addrmod3(cond | L | B7 | S6 | B4, dst, src); 1151 addrmod3(cond | L | B7 | S6 | B4, dst, src);
1152 } 1152 }
1153 1153
1154 1154
1155 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { 1155 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
1156 addrmod3(cond | L | B7 | S6 | H | B4, dst, src); 1156 addrmod3(cond | L | B7 | S6 | H | B4, dst, src);
1157 } 1157 }
1158 1158
1159 1159
1160 void Assembler::ldrd(Register dst, const MemOperand& src, Condition cond) {
1161 ASSERT(src.rm().is(no_reg));
1162 #ifdef CAN_USE_ARMV7_INSTRUCTIONS
1163 addrmod3(cond | B7 | B6 | B4, dst, src);
1164 #else
1165 ldr(dst, src, cond);
1166 MemOperand src1(src);
1167 src1.set_offset(src1.offset() + 4);
1168 Register dst1(dst);
1169 dst1.code_ = dst1.code_ + 1;
1170 ldr(dst1, src1, cond);
1171 #endif
1172 }
1173
1174
1175 void Assembler::strd(Register src, const MemOperand& dst, Condition cond) {
1176 ASSERT(dst.rm().is(no_reg));
1177 #ifdef CAN_USE_ARMV7_INSTRUCTIONS
1178 addrmod3(cond | B7 | B6 | B5 | B4, src, dst);
1179 #else
1180 str(src, dst, cond);
1181 MemOperand dst1(dst);
1182 dst1.set_offset(dst1.offset() + 4);
1183 Register src1(src);
1184 src1.code_ = src1.code_ + 1;
1185 str(src1, dst1, cond);
1186 #endif
1187 }
1188
1160 // Load/Store multiple instructions. 1189 // Load/Store multiple instructions.
1161 void Assembler::ldm(BlockAddrMode am, 1190 void Assembler::ldm(BlockAddrMode am,
1162 Register base, 1191 Register base,
1163 RegList dst, 1192 RegList dst,
1164 Condition cond) { 1193 Condition cond) {
1165 // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable. 1194 // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable.
1166 ASSERT(base.is(sp) || (dst & sp.bit()) == 0); 1195 ASSERT(base.is(sp) || (dst & sp.bit()) == 0);
1167 1196
1168 addrmod4(cond | B27 | am | L, base, dst); 1197 addrmod4(cond | B27 | am | L, base, dst);
1169 1198
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2026 bind(&after_pool); 2055 bind(&after_pool);
2027 } 2056 }
2028 2057
2029 // Since a constant pool was just emitted, move the check offset forward by 2058 // Since a constant pool was just emitted, move the check offset forward by
2030 // the standard interval. 2059 // the standard interval.
2031 next_buffer_check_ = pc_offset() + kCheckConstInterval; 2060 next_buffer_check_ = pc_offset() + kCheckConstInterval;
2032 } 2061 }
2033 2062
2034 2063
2035 } } // namespace v8::internal 2064 } } // namespace v8::internal
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