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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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98 | 98 |
99 | 99 |
100 Address* RelocInfo::target_reference_address() { | 100 Address* RelocInfo::target_reference_address() { |
101 ASSERT(rmode_ == EXTERNAL_REFERENCE); | 101 ASSERT(rmode_ == EXTERNAL_REFERENCE); |
102 return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_)); | 102 return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_)); |
103 } | 103 } |
104 | 104 |
105 | 105 |
106 Address RelocInfo::call_address() { | 106 Address RelocInfo::call_address() { |
107 ASSERT(IsCallInstruction()); | 107 ASSERT(IsCallInstruction()); |
108 UNIMPLEMENTED(); | 108 // The 2 instructions offset assumes patched return sequence. |
109 return NULL; | 109 ASSERT(IsJSReturn(rmode())); |
| 110 return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize); |
110 } | 111 } |
111 | 112 |
112 | 113 |
113 void RelocInfo::set_call_address(Address target) { | 114 void RelocInfo::set_call_address(Address target) { |
114 ASSERT(IsCallInstruction()); | 115 ASSERT(IsCallInstruction()); |
115 UNIMPLEMENTED(); | 116 // The 2 instructions offset assumes patched return sequence. |
| 117 ASSERT(IsJSReturn(rmode())); |
| 118 Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target; |
116 } | 119 } |
117 | 120 |
118 | 121 |
119 Object* RelocInfo::call_object() { | 122 Object* RelocInfo::call_object() { |
120 ASSERT(IsCallInstruction()); | 123 return *call_object_address(); |
121 UNIMPLEMENTED(); | |
122 return NULL; | |
123 } | 124 } |
124 | 125 |
125 | 126 |
126 Object** RelocInfo::call_object_address() { | 127 Object** RelocInfo::call_object_address() { |
127 ASSERT(IsCallInstruction()); | 128 ASSERT(IsCallInstruction()); |
128 UNIMPLEMENTED(); | 129 // The 2 instructions offset assumes patched return sequence. |
129 return NULL; | 130 ASSERT(IsJSReturn(rmode())); |
| 131 return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize); |
130 } | 132 } |
131 | 133 |
132 | 134 |
133 void RelocInfo::set_call_object(Object* target) { | 135 void RelocInfo::set_call_object(Object* target) { |
134 ASSERT(IsCallInstruction()); | 136 *call_object_address() = target; |
135 UNIMPLEMENTED(); | |
136 } | 137 } |
137 | 138 |
138 | 139 |
139 bool RelocInfo::IsCallInstruction() { | 140 bool RelocInfo::IsCallInstruction() { |
140 UNIMPLEMENTED(); | 141 // On ARM a "call instruction" is actually two instructions. |
141 return false; | 142 // mov lr, pc |
| 143 // ldr pc, [pc, #XXX] |
| 144 return (Assembler::instr_at(pc_) == kMovLrPc) |
| 145 && ((Assembler::instr_at(pc_ + Assembler::kInstrSize) & kLdrPCPattern) |
| 146 == kLdrPCPattern); |
142 } | 147 } |
143 | 148 |
144 | 149 |
145 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { | 150 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { |
146 rm_ = no_reg; | 151 rm_ = no_reg; |
147 imm32_ = immediate; | 152 imm32_ = immediate; |
148 rmode_ = rmode; | 153 rmode_ = rmode; |
149 } | 154 } |
150 | 155 |
151 | 156 |
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241 // CPU::FlushICache(pc, sizeof(target)); | 246 // CPU::FlushICache(pc, sizeof(target)); |
242 // However, on ARM, no instruction was actually patched by the assignment | 247 // However, on ARM, no instruction was actually patched by the assignment |
243 // above; the target address is not part of an instruction, it is patched in | 248 // above; the target address is not part of an instruction, it is patched in |
244 // the constant pool and is read via a data access; the instruction accessing | 249 // the constant pool and is read via a data access; the instruction accessing |
245 // this address in the constant pool remains unchanged. | 250 // this address in the constant pool remains unchanged. |
246 } | 251 } |
247 | 252 |
248 } } // namespace v8::internal | 253 } } // namespace v8::internal |
249 | 254 |
250 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ | 255 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ |
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