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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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452 | 452 |
453 // Data-processing instructions | 453 // Data-processing instructions |
454 void and_(Register dst, Register src1, const Operand& src2, | 454 void and_(Register dst, Register src1, const Operand& src2, |
455 SBit s = LeaveCC, Condition cond = al); | 455 SBit s = LeaveCC, Condition cond = al); |
456 | 456 |
457 void eor(Register dst, Register src1, const Operand& src2, | 457 void eor(Register dst, Register src1, const Operand& src2, |
458 SBit s = LeaveCC, Condition cond = al); | 458 SBit s = LeaveCC, Condition cond = al); |
459 | 459 |
460 void sub(Register dst, Register src1, const Operand& src2, | 460 void sub(Register dst, Register src1, const Operand& src2, |
461 SBit s = LeaveCC, Condition cond = al); | 461 SBit s = LeaveCC, Condition cond = al); |
| 462 void sub(Register dst, Register src1, Register src2, |
| 463 SBit s = LeaveCC, Condition cond = al) { |
| 464 sub(dst, src1, Operand(src2), s, cond); |
| 465 } |
462 | 466 |
463 void rsb(Register dst, Register src1, const Operand& src2, | 467 void rsb(Register dst, Register src1, const Operand& src2, |
464 SBit s = LeaveCC, Condition cond = al); | 468 SBit s = LeaveCC, Condition cond = al); |
465 | 469 |
466 void add(Register dst, Register src1, const Operand& src2, | 470 void add(Register dst, Register src1, const Operand& src2, |
467 SBit s = LeaveCC, Condition cond = al); | 471 SBit s = LeaveCC, Condition cond = al); |
468 | 472 |
469 void adc(Register dst, Register src1, const Operand& src2, | 473 void adc(Register dst, Register src1, const Operand& src2, |
470 SBit s = LeaveCC, Condition cond = al); | 474 SBit s = LeaveCC, Condition cond = al); |
471 | 475 |
472 void sbc(Register dst, Register src1, const Operand& src2, | 476 void sbc(Register dst, Register src1, const Operand& src2, |
473 SBit s = LeaveCC, Condition cond = al); | 477 SBit s = LeaveCC, Condition cond = al); |
474 | 478 |
475 void rsc(Register dst, Register src1, const Operand& src2, | 479 void rsc(Register dst, Register src1, const Operand& src2, |
476 SBit s = LeaveCC, Condition cond = al); | 480 SBit s = LeaveCC, Condition cond = al); |
477 | 481 |
478 void tst(Register src1, const Operand& src2, Condition cond = al); | 482 void tst(Register src1, const Operand& src2, Condition cond = al); |
| 483 void tst(Register src1, Register src2, Condition cond = al) { |
| 484 tst(src1, Operand(src2), cond); |
| 485 } |
479 | 486 |
480 void teq(Register src1, const Operand& src2, Condition cond = al); | 487 void teq(Register src1, const Operand& src2, Condition cond = al); |
481 | 488 |
482 void cmp(Register src1, const Operand& src2, Condition cond = al); | 489 void cmp(Register src1, const Operand& src2, Condition cond = al); |
| 490 void cmp(Register src1, Register src2, Condition cond = al) { |
| 491 cmp(src1, Operand(src2), cond); |
| 492 } |
483 | 493 |
484 void cmn(Register src1, const Operand& src2, Condition cond = al); | 494 void cmn(Register src1, const Operand& src2, Condition cond = al); |
485 | 495 |
486 void orr(Register dst, Register src1, const Operand& src2, | 496 void orr(Register dst, Register src1, const Operand& src2, |
487 SBit s = LeaveCC, Condition cond = al); | 497 SBit s = LeaveCC, Condition cond = al); |
| 498 void orr(Register dst, Register src1, Register src2, |
| 499 SBit s = LeaveCC, Condition cond = al) { |
| 500 orr(dst, src1, Operand(src2), s, cond); |
| 501 } |
488 | 502 |
489 void mov(Register dst, const Operand& src, | 503 void mov(Register dst, const Operand& src, |
490 SBit s = LeaveCC, Condition cond = al); | 504 SBit s = LeaveCC, Condition cond = al); |
| 505 void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) { |
| 506 mov(dst, Operand(src), s, cond); |
| 507 } |
491 | 508 |
492 void bic(Register dst, Register src1, const Operand& src2, | 509 void bic(Register dst, Register src1, const Operand& src2, |
493 SBit s = LeaveCC, Condition cond = al); | 510 SBit s = LeaveCC, Condition cond = al); |
494 | 511 |
495 void mvn(Register dst, const Operand& src, | 512 void mvn(Register dst, const Operand& src, |
496 SBit s = LeaveCC, Condition cond = al); | 513 SBit s = LeaveCC, Condition cond = al); |
497 | 514 |
498 // Multiply instructions | 515 // Multiply instructions |
499 | 516 |
500 void mla(Register dst, Register src1, Register src2, Register srcA, | 517 void mla(Register dst, Register src1, Register src2, Register srcA, |
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759 | 776 |
760 // Block the emission of the constant pool before pc_offset | 777 // Block the emission of the constant pool before pc_offset |
761 void BlockConstPoolBefore(int pc_offset) { | 778 void BlockConstPoolBefore(int pc_offset) { |
762 if (no_const_pool_before_ < pc_offset) no_const_pool_before_ = pc_offset; | 779 if (no_const_pool_before_ < pc_offset) no_const_pool_before_ = pc_offset; |
763 } | 780 } |
764 }; | 781 }; |
765 | 782 |
766 } } // namespace v8::internal | 783 } } // namespace v8::internal |
767 | 784 |
768 #endif // V8_ASSEMBLER_ARM_H_ | 785 #endif // V8_ASSEMBLER_ARM_H_ |
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