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1 // Copyright 2006-2009 the V8 project authors. All rights reserved. | 1 // Copyright 2006-2009 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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110 } | 110 } |
111 | 111 |
112 | 112 |
113 void MacroAssembler::Call(intptr_t target, RelocInfo::Mode rmode, | 113 void MacroAssembler::Call(intptr_t target, RelocInfo::Mode rmode, |
114 Condition cond) { | 114 Condition cond) { |
115 #if USE_BLX | 115 #if USE_BLX |
116 // On ARMv5 and after the recommended call sequence is: | 116 // On ARMv5 and after the recommended call sequence is: |
117 // ldr ip, [pc, #...] | 117 // ldr ip, [pc, #...] |
118 // blx ip | 118 // blx ip |
119 | 119 |
120 // The two instructions (ldr and blx) could be separated by a literal | 120 { |
121 // pool and the code would still work. The issue comes from the | 121 // The two instructions (ldr and blx) could be separated by a constant |
122 // patching code which expect the ldr to be just above the blx. | 122 // pool and the code would still work. The issue comes from the |
123 BlockConstPoolFor(2); | 123 // patching code which expect the ldr to be just above the blx. |
124 // Statement positions are expected to be recorded when the target | 124 BlockConstPoolScope block_const_pool(this); |
125 // address is loaded. The mov method will automatically record | 125 // Statement positions are expected to be recorded when the target |
126 // positions when pc is the target, since this is not the case here | 126 // address is loaded. The mov method will automatically record |
127 // we have to do it explicitly. | 127 // positions when pc is the target, since this is not the case here |
128 WriteRecordedPositions(); | 128 // we have to do it explicitly. |
| 129 WriteRecordedPositions(); |
129 | 130 |
130 mov(ip, Operand(target, rmode), LeaveCC, cond); | 131 mov(ip, Operand(target, rmode), LeaveCC, cond); |
131 blx(ip, cond); | 132 blx(ip, cond); |
| 133 } |
132 | 134 |
133 ASSERT(kCallTargetAddressOffset == 2 * kInstrSize); | 135 ASSERT(kCallTargetAddressOffset == 2 * kInstrSize); |
134 #else | 136 #else |
135 // Set lr for return at current pc + 8. | 137 // Set lr for return at current pc + 8. |
136 mov(lr, Operand(pc), LeaveCC, cond); | 138 mov(lr, Operand(pc), LeaveCC, cond); |
137 // Emit a ldr<cond> pc, [pc + offset of target in constant pool]. | 139 // Emit a ldr<cond> pc, [pc + offset of target in constant pool]. |
138 mov(pc, Operand(target, rmode), LeaveCC, cond); | 140 mov(pc, Operand(target, rmode), LeaveCC, cond); |
139 | 141 |
140 ASSERT(kCallTargetAddressOffset == kInstrSize); | 142 ASSERT(kCallTargetAddressOffset == kInstrSize); |
141 #endif | 143 #endif |
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1660 } | 1662 } |
1661 | 1663 |
1662 | 1664 |
1663 void CodePatcher::Emit(Address addr) { | 1665 void CodePatcher::Emit(Address addr) { |
1664 masm()->emit(reinterpret_cast<Instr>(addr)); | 1666 masm()->emit(reinterpret_cast<Instr>(addr)); |
1665 } | 1667 } |
1666 #endif // ENABLE_DEBUGGER_SUPPORT | 1668 #endif // ENABLE_DEBUGGER_SUPPORT |
1667 | 1669 |
1668 | 1670 |
1669 } } // namespace v8::internal | 1671 } } // namespace v8::internal |
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