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1 // Copyright 2009 the V8 project authors. All rights reserved. | 1 // Copyright 2009 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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81 { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" }, | 81 { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" }, |
82 { 0x2B, REG_OPER_OP_ORDER, "sub" }, | 82 { 0x2B, REG_OPER_OP_ORDER, "sub" }, |
83 { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" }, | 83 { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" }, |
84 { 0x31, OPER_REG_OP_ORDER, "xor" }, | 84 { 0x31, OPER_REG_OP_ORDER, "xor" }, |
85 { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" }, | 85 { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" }, |
86 { 0x33, REG_OPER_OP_ORDER, "xor" }, | 86 { 0x33, REG_OPER_OP_ORDER, "xor" }, |
87 { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" }, | 87 { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" }, |
88 { 0x39, OPER_REG_OP_ORDER, "cmp" }, | 88 { 0x39, OPER_REG_OP_ORDER, "cmp" }, |
89 { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" }, | 89 { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" }, |
90 { 0x3B, REG_OPER_OP_ORDER, "cmp" }, | 90 { 0x3B, REG_OPER_OP_ORDER, "cmp" }, |
91 { 0x8D, REG_OPER_OP_ORDER, "lea" }, | 91 { 0x63, REG_OPER_OP_ORDER, "movsxlq" }, |
92 { 0x84, BYTE_REG_OPER_OP_ORDER, "test" }, | 92 { 0x84, BYTE_REG_OPER_OP_ORDER, "test" }, |
93 { 0x85, REG_OPER_OP_ORDER, "test" }, | 93 { 0x85, REG_OPER_OP_ORDER, "test" }, |
94 { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" }, | 94 { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" }, |
95 { 0x87, REG_OPER_OP_ORDER, "xchg" }, | 95 { 0x87, REG_OPER_OP_ORDER, "xchg" }, |
96 { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" }, | 96 { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" }, |
97 { 0x89, OPER_REG_OP_ORDER, "mov" }, | 97 { 0x89, OPER_REG_OP_ORDER, "mov" }, |
98 { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" }, | 98 { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" }, |
99 { 0x8B, REG_OPER_OP_ORDER, "mov" }, | 99 { 0x8B, REG_OPER_OP_ORDER, "mov" }, |
| 100 { 0x8D, REG_OPER_OP_ORDER, "lea" }, |
100 { -1, UNSET_OP_ORDER, "" } | 101 { -1, UNSET_OP_ORDER, "" } |
101 }; | 102 }; |
102 | 103 |
103 | 104 |
104 static ByteMnemonic zero_operands_instr[] = { | 105 static ByteMnemonic zero_operands_instr[] = { |
105 { 0xC3, UNSET_OP_ORDER, "ret" }, | 106 { 0xC3, UNSET_OP_ORDER, "ret" }, |
106 { 0xC9, UNSET_OP_ORDER, "leave" }, | 107 { 0xC9, UNSET_OP_ORDER, "leave" }, |
107 { 0x90, UNSET_OP_ORDER, "nop" }, | 108 { 0x90, UNSET_OP_ORDER, "nop" }, |
108 { 0xF4, UNSET_OP_ORDER, "hlt" }, | 109 { 0xF4, UNSET_OP_ORDER, "hlt" }, |
109 { 0xCC, UNSET_OP_ORDER, "int3" }, | 110 { 0xCC, UNSET_OP_ORDER, "int3" }, |
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1582 fprintf(f, "%02x", *bp); | 1583 fprintf(f, "%02x", *bp); |
1583 } | 1584 } |
1584 for (int i = 6 - (pc - prev_pc); i >= 0; i--) { | 1585 for (int i = 6 - (pc - prev_pc); i >= 0; i--) { |
1585 fprintf(f, " "); | 1586 fprintf(f, " "); |
1586 } | 1587 } |
1587 fprintf(f, " %s\n", buffer.start()); | 1588 fprintf(f, " %s\n", buffer.start()); |
1588 } | 1589 } |
1589 } | 1590 } |
1590 | 1591 |
1591 } // namespace disasm | 1592 } // namespace disasm |
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