X64: Add fix of issue 392 to X64

src/x64/disasm-x64.cc

Index: src/x64/disasm-x64.cc
===================================================================
--- src/x64/disasm-x64.cc	(revision 2593)
+++ src/x64/disasm-x64.cc	(working copy)
@@ -139,7 +139,7 @@
 
 
 static const char* conditional_code_suffix[] = {
-  "o", "no", "c", "nc", "z", "nz", "a", "na",
+  "o", "no", "c", "nc", "z", "nz", "na", "a",
   "s", "ns", "pe", "po", "l", "ge", "le", "g"
 };
 
@@ -252,6 +252,24 @@
 
 static InstructionTable instruction_table;
 
+static InstructionDesc cmov_instructions[16] = {
+  {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
+};
 
 //------------------------------------------------------------------------------
 // DisassemblerX64 implementation.
@@ -533,7 +551,7 @@
       value = 0;  // Initialize variables on all paths to satisfy the compiler.
       count = 0;
   }
-  AppendToBuffer(V8_PTR_PREFIX"x", value);
+  AppendToBuffer("%" V8_PTR_PREFIX "x", value);
   return count;
 }
 
@@ -966,6 +984,13 @@
     // RDTSC or CPUID
     AppendToBuffer("%s", mnemonic);
 
+  } else if ((opcode & 0xF0) == 0x40) {
+    // CMOVcc: conditional move.
+    int condition = opcode & 0x0F;
+    const InstructionDesc& idesc = cmov_instructions[condition];
+    byte_size_operand_ = idesc.byte_size_operation;
+    current += PrintOperands(idesc.mnem, idesc.op_order_, current);
+
   } else if ((opcode & 0xF0) == 0x80) {
     // Jcc: Conditional jump (branch).
     current = data + JumpConditional(data);
@@ -1350,9 +1375,9 @@
             const char* memory_location = NameOfAddress(
                 reinterpret_cast<byte*>(
                     *reinterpret_cast<int32_t*>(data + 1)));
-            if (*data == 0xA3) {  // Opcode 0xA3
+            if (*data == 0xA1) {  // Opcode 0xA1
               AppendToBuffer("movzxlq rax,(%s)", memory_location);
-            } else {  // Opcode 0xA1
+            } else {  // Opcode 0xA3
               AppendToBuffer("movzxlq (%s),rax", memory_location);
             }
             data += 5;
@@ -1362,9 +1387,9 @@
             // New x64 instruction mov rax,(imm_64).
             const char* memory_location = NameOfAddress(
                 *reinterpret_cast<byte**>(data + 1));
-            if (*data == 0xA3) {  // Opcode 0xA3
+            if (*data == 0xA1) {  // Opcode 0xA1
               AppendToBuffer("movq rax,(%s)", memory_location);
-            } else {  // Opcode 0xA1
+            } else {  // Opcode 0xA3
               AppendToBuffer("movq (%s),rax", memory_location);
             }
             data += 9;