X64: Add fix of issue 392 to X64

src/x64/disasm-x64.cc

 // Copyright 2009 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 121 matching lines @@
   { 0x1D, UNSET_OP_ORDER, "sbb" },
   { 0x25, UNSET_OP_ORDER, "and" },
   { 0x2D, UNSET_OP_ORDER, "sub" },
   { 0x35, UNSET_OP_ORDER, "xor" },
   { 0x3D, UNSET_OP_ORDER, "cmp" },
   { -1, UNSET_OP_ORDER, "" }
 };
 
 
 static const char* conditional_code_suffix[] = {
-  "o", "no", "c", "nc", "z", "nz", "a", "na",
+  "o", "no", "c", "nc", "z", "nz", "na", "a",
   "s", "ns", "pe", "po", "l", "ge", "le", "g"
 };
 
 
 enum InstructionType {
   NO_INSTR,
   ZERO_OPERANDS_INSTR,
   TWO_OPERANDS_INSTR,
   JUMP_CONDITIONAL_SHORT_INSTR,
   REGISTER_INSTR,
@@ skipping 92 matching lines @@
     InstructionDesc* id = &instructions_[b];
     assert(id->type == NO_INSTR);  // Information already entered
     id->mnem = NULL;  // Computed depending on condition code.
     id->type = JUMP_CONDITIONAL_SHORT_INSTR;
   }
 }
 
 
 static InstructionTable instruction_table;
 
+static InstructionDesc cmov_instructions[16] = {
+  {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+  {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
+};
 
 //------------------------------------------------------------------------------
 // DisassemblerX64 implementation.
 
 enum UnimplementedOpcodeAction {
   CONTINUE_ON_UNIMPLEMENTED_OPCODE,
   ABORT_ON_UNIMPLEMENTED_OPCODE
 };
 
 // A new DisassemblerX64 object is created to disassemble each instruction.
@@ skipping 261 matching lines @@
       break;
     case QUADWORD_SIZE:
       value = *reinterpret_cast<int32_t*>(data);
       count = 4;
       break;
     default:
       UNREACHABLE();
       value = 0;  // Initialize variables on all paths to satisfy the compiler.
       count = 0;
   }
-  AppendToBuffer(V8_PTR_PREFIX"x", value);
+  AppendToBuffer("%" V8_PTR_PREFIX "x", value);
   return count;
 }
 
 
 int DisassemblerX64::PrintRightOperand(byte* modrmp) {
   return PrintRightOperandHelper(modrmp,
                                  &DisassemblerX64::NameOfCPURegister);
 }
 
 
@@ skipping 412 matching lines @@
       current += 1;
     } else if (mod == 2) {  // 32-bit displacement.
       current += 4;
     }  // else no immediate displacement.
     AppendToBuffer("nop");
 
   } else  if (opcode == 0xA2 || opcode == 0x31) {
     // RDTSC or CPUID
     AppendToBuffer("%s", mnemonic);
 
+  } else if ((opcode & 0xF0) == 0x40) {
+    // CMOVcc: conditional move.
+    int condition = opcode & 0x0F;
+    const InstructionDesc& idesc = cmov_instructions[condition];
+    byte_size_operand_ = idesc.byte_size_operation;
+    current += PrintOperands(idesc.mnem, idesc.op_order_, current);
+
   } else if ((opcode & 0xF0) == 0x80) {
     // Jcc: Conditional jump (branch).
     current = data + JumpConditional(data);
 
   } else if (opcode == 0xBE || opcode == 0xBF || opcode == 0xB6 ||
              opcode == 0xB7 || opcode == 0xAF) {
     // Size-extending moves, IMUL.
     current += PrintOperands(mnemonic, REG_OPER_OP_ORDER, current);
 
   } else if ((opcode & 0xF0) == 0x90) {
@@ skipping 364 matching lines @@
         data += 2;
         break;
 
       case 0xA1:  // Fall through.
       case 0xA3:
         switch (operand_size()) {
           case DOUBLEWORD_SIZE: {
             const char* memory_location = NameOfAddress(
                 reinterpret_cast<byte*>(
                     *reinterpret_cast<int32_t*>(data + 1)));
-            if (*data == 0xA3) {  // Opcode 0xA3
+            if (*data == 0xA1) {  // Opcode 0xA1
               AppendToBuffer("movzxlq rax,(%s)", memory_location);
-            } else {  // Opcode 0xA1
+            } else {  // Opcode 0xA3
               AppendToBuffer("movzxlq (%s),rax", memory_location);
             }
             data += 5;
             break;
           }
           case QUADWORD_SIZE: {
             // New x64 instruction mov rax,(imm_64).
             const char* memory_location = NameOfAddress(
                 *reinterpret_cast<byte**>(data + 1));
-            if (*data == 0xA3) {  // Opcode 0xA3
+            if (*data == 0xA1) {  // Opcode 0xA1
               AppendToBuffer("movq rax,(%s)", memory_location);
-            } else {  // Opcode 0xA1
+            } else {  // Opcode 0xA3
               AppendToBuffer("movq (%s),rax", memory_location);
             }
             data += 9;
             break;
           }
           default:
             UnimplementedInstruction();
             data += 2;
         }
         break;
@@ skipping 179 matching lines @@
       fprintf(f, "%02x", *bp);
     }
     for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
       fprintf(f, "  ");
     }
     fprintf(f, "  %s\n", buffer.start());
   }
 }
 
 }  // namespace disasm