Add support for bkpt instruction...

src/arm/disasm-arm.cc

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 431 matching lines @@
       } else if ((format[3] == '1') && (format[4] == '6')) {
         ASSERT(STRING_STARTS_WITH(format, "off16to20"));
         out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                            "%d", instr->Bits(20, 16) +1);
         return 9;
       } else if (format[3] == '7') {
         ASSERT(STRING_STARTS_WITH(format, "off7to11"));
         out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                             "%d", instr->ShiftAmountField());
         return 8;
+      } else if (format[3] == '0') {
+        // 'off0to3and8to19 16-bit immediate encoded in bits 19-8 and 3-0.
+        ASSERT(STRING_STARTS_WITH(format, "off0to3and8to19"));
+        out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                            "%d",
+                                            (instr->Bits(19, 8) << 4) +
+                                                instr->Bits(3, 0));
+        return 15;
       }
       // 'off8: 8-bit offset for extra load and store instructions
       ASSERT(STRING_STARTS_WITH(format, "off8"));
       int offs8 = (instr->ImmedHField() << 4) | instr->ImmedLField();
       out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                            "%d", offs8);
       return 4;
     }
     case 'p': {  // 'pu: P and U bits for load and store instructions
       ASSERT(STRING_STARTS_WITH(format, "pu"));
@@ skipping 181 matching lines @@
           break;
         }
         default: {
           // The PU field is a 2-bit field.
           UNREACHABLE();
           break;
         }
       }
       return;
     }
+  } else if ((type == 0) && instr->IsMiscType0()) {

[Erik Corry, 2010/04/08 12:56:30]

This is a little strange to me, but if it matches the manual organization then
I'm fine with it.

[Søren Thygesen Gjesse, 2010/04/08 13:29:06]

Section A5.2 in ARM® Architecture Reference Manual ARM®v7-A and ARM®v7-R
edition.

+    if (instr->Bits(22, 21) == 1) {
+      switch (instr->Bits(7, 4)) {
+        case BX:
+          Format(instr, "bx'cond 'rm");
+          break;
+        case BLX:
+          Format(instr, "blx'cond 'rm");
+          break;
+        case BKPT:
+          Format(instr, "bkpt 'off0to3and8to19");
+          break;
+        default:
+          Unknown(instr);  // not used by V8
+          break;
+      }
+    } else if (instr->Bits(22, 21) == 3) {
+      switch (instr->Bits(7, 4)) {
+        case CLZ:
+          Format(instr, "clz'cond 'rd, 'rm");
+          break;
+        default:
+          Unknown(instr);  // not used by V8
+          break;
+      }
+    } else {
+      Unknown(instr);  // not used by V8
+    }
   } else {
     switch (instr->OpcodeField()) {
       case AND: {
         Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
         break;
       }
       case EOR: {
         Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
         break;
       }
@@ skipping 26 matching lines @@
           Format(instr, "tst'cond 'rn, 'shift_op");
         } else {
           Unknown(instr);  // not used by V8
         }
         break;
       }
       case TEQ: {
         if (instr->HasS()) {
           Format(instr, "teq'cond 'rn, 'shift_op");
         } else {
-          switch (instr->Bits(7, 4)) {
-            case BX:
-              Format(instr, "bx'cond 'rm");
-              break;
-            case BLX:
-              Format(instr, "blx'cond 'rm");
-              break;
-            default:
-              Unknown(instr);  // not used by V8
-              break;
-          }
+          Unknown(instr);  // not used by V8

[Erik Corry, 2010/04/08 12:56:30]

UNREACHABLE();  // Handled by IsMiscType0 code above.

[Søren Thygesen Gjesse, 2010/04/08 13:29:06]

Done.

         }
         break;
       }
       case CMP: {
         if (instr->HasS()) {
           Format(instr, "cmp'cond 'rn, 'shift_op");
         } else {
           Unknown(instr);  // not used by V8
         }
         break;
       }
       case CMN: {
         if (instr->HasS()) {
           Format(instr, "cmn'cond 'rn, 'shift_op");
         } else {
-          switch (instr->Bits(7, 4)) {
-            case CLZ:
-              Format(instr, "clz'cond 'rd, 'rm");
-              break;
-            default:
-              Unknown(instr);  // not used by V8
-              break;
-          }
+          Unknown(instr);  // not used by V8

[Erik Corry, 2010/04/08 12:56:30]

And here.

[Søren Thygesen Gjesse, 2010/04/08 13:29:06]

Done.

         }
         break;
       }
       case ORR: {
         Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
         break;
       }
       case MOV: {
         Format(instr, "mov'cond's 'rd, 'shift_op");
         break;
@@ skipping 537 matching lines @@
     buffer[0] = '\0';
     byte* prev_pc = pc;
     pc += d.InstructionDecode(buffer, pc);
     fprintf(f, "%p    %08x      %s\n",
             prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm