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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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144 CMP = 10, // Compare | 144 CMP = 10, // Compare |
145 CMN = 11, // Compare Negated | 145 CMN = 11, // Compare Negated |
146 ORR = 12, // Logical (inclusive) OR | 146 ORR = 12, // Logical (inclusive) OR |
147 MOV = 13, // Move | 147 MOV = 13, // Move |
148 BIC = 14, // Bit Clear | 148 BIC = 14, // Bit Clear |
149 MVN = 15, // Move Not | 149 MVN = 15, // Move Not |
150 max_operand = 16 | 150 max_operand = 16 |
151 }; | 151 }; |
152 | 152 |
153 | 153 |
154 // Some special instructions encoded as a TEQ with S=0 (bit 20). | 154 // The bits for bit 7-4 for some type 0 miscellaneous instructions. |
155 enum Opcode9Bits { | 155 enum MiscInstructionsBits74 { |
| 156 // With bits 22-21 01. |
156 BX = 1, | 157 BX = 1, |
157 BXJ = 2, | 158 BXJ = 2, |
158 BLX = 3, | 159 BLX = 3, |
159 BKPT = 7 | 160 BKPT = 7, |
160 }; | |
161 | 161 |
162 | 162 // With bits 22-21 11. |
163 // Some special instructions encoded as a CMN with S=0 (bit 20). | |
164 enum Opcode11Bits { | |
165 CLZ = 1 | 163 CLZ = 1 |
166 }; | 164 }; |
167 | 165 |
168 | 166 |
169 // S | |
170 | |
171 | |
172 // Shifter types for Data-processing operands as defined in section A5.1.2. | 167 // Shifter types for Data-processing operands as defined in section A5.1.2. |
173 enum Shift { | 168 enum Shift { |
174 no_shift = -1, | 169 no_shift = -1, |
175 LSL = 0, // Logical shift left | 170 LSL = 0, // Logical shift left |
176 LSR = 1, // Logical shift right | 171 LSR = 1, // Logical shift right |
177 ASR = 2, // Arithmetic shift right | 172 ASR = 2, // Arithmetic shift right |
178 ROR = 3, // Rotate right | 173 ROR = 3, // Rotate right |
179 max_shift = 4 | 174 max_shift = 4 |
180 }; | 175 }; |
181 | 176 |
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303 | 298 |
304 // Fields used in Software interrupt instructions | 299 // Fields used in Software interrupt instructions |
305 inline SoftwareInterruptCodes SwiField() const { | 300 inline SoftwareInterruptCodes SwiField() const { |
306 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); | 301 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); |
307 } | 302 } |
308 | 303 |
309 // Test for special encodings of type 0 instructions (extra loads and stores, | 304 // Test for special encodings of type 0 instructions (extra loads and stores, |
310 // as well as multiplications). | 305 // as well as multiplications). |
311 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } | 306 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } |
312 | 307 |
| 308 // Test for miscellaneous instructions encodings of type 0 instructions. |
| 309 inline bool IsMiscType0() const { return (Bit(24) == 1) |
| 310 && (Bit(23) == 0) |
| 311 && (Bit(20) == 0) |
| 312 && ((Bit(4) == 0) |
| 313 || ((Bit(7) == 0) |
| 314 && (Bit(4) == 1))); } |
| 315 |
313 // Special accessors that test for existence of a value. | 316 // Special accessors that test for existence of a value. |
314 inline bool HasS() const { return SField() == 1; } | 317 inline bool HasS() const { return SField() == 1; } |
315 inline bool HasB() const { return BField() == 1; } | 318 inline bool HasB() const { return BField() == 1; } |
316 inline bool HasW() const { return WField() == 1; } | 319 inline bool HasW() const { return WField() == 1; } |
317 inline bool HasL() const { return LField() == 1; } | 320 inline bool HasL() const { return LField() == 1; } |
318 inline bool HasU() const { return UField() == 1; } | 321 inline bool HasU() const { return UField() == 1; } |
319 inline bool HasSign() const { return SignField() == 1; } | 322 inline bool HasSign() const { return SignField() == 1; } |
320 inline bool HasH() const { return HField() == 1; } | 323 inline bool HasH() const { return HField() == 1; } |
321 inline bool HasLink() const { return LinkField() == 1; } | 324 inline bool HasLink() const { return LinkField() == 1; } |
322 | 325 |
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363 static int Number(const char* name, bool* is_double); | 366 static int Number(const char* name, bool* is_double); |
364 | 367 |
365 private: | 368 private: |
366 static const char* names_[kNumVFPRegisters]; | 369 static const char* names_[kNumVFPRegisters]; |
367 }; | 370 }; |
368 | 371 |
369 | 372 |
370 } } // namespace assembler::arm | 373 } } // namespace assembler::arm |
371 | 374 |
372 #endif // V8_ARM_CONSTANTS_ARM_H_ | 375 #endif // V8_ARM_CONSTANTS_ARM_H_ |
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