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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
| 6 // met: | 6 // met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 514 // Conditional moves. | 514 // Conditional moves. |
| 515 void cmovq(Condition cc, Register dst, Register src); | 515 void cmovq(Condition cc, Register dst, Register src); |
| 516 void cmovq(Condition cc, Register dst, const Operand& src); | 516 void cmovq(Condition cc, Register dst, const Operand& src); |
| 517 void cmovl(Condition cc, Register dst, Register src); | 517 void cmovl(Condition cc, Register dst, Register src); |
| 518 void cmovl(Condition cc, Register dst, const Operand& src); | 518 void cmovl(Condition cc, Register dst, const Operand& src); |
| 519 | 519 |
| 520 // Exchange two registers | 520 // Exchange two registers |
| 521 void xchg(Register dst, Register src); | 521 void xchg(Register dst, Register src); |
| 522 | 522 |
| 523 // Arithmetics | 523 // Arithmetics |
| 524 void addq(Register dst, Register src) { | |
| 525 arithmetic_op(0x03, dst, src); | |
| 526 } | |
| 527 | |
| 528 void addl(Register dst, Register src) { | 524 void addl(Register dst, Register src) { |
| 529 arithmetic_op_32(0x03, dst, src); | 525 arithmetic_op_32(0x03, dst, src); |
| 530 } | 526 } |
| 531 | 527 |
| 532 void addl(Register dst, Immediate src) { | 528 void addl(Register dst, Immediate src) { |
| 533 immediate_arithmetic_op_32(0x0, dst, src); | 529 immediate_arithmetic_op_32(0x0, dst, src); |
| 534 } | 530 } |
| 535 | 531 |
| 532 void addl(Register dst, const Operand& src) { |
| 533 arithmetic_op_32(0x03, dst, src); |
| 534 } |
| 535 |
| 536 void addl(const Operand& dst, Immediate src) { | 536 void addl(const Operand& dst, Immediate src) { |
| 537 immediate_arithmetic_op_32(0x0, dst, src); | 537 immediate_arithmetic_op_32(0x0, dst, src); |
| 538 } | 538 } |
| 539 | 539 |
| 540 void addq(Register dst, Register src) { |
| 541 arithmetic_op(0x03, dst, src); |
| 542 } |
| 543 |
| 540 void addq(Register dst, const Operand& src) { | 544 void addq(Register dst, const Operand& src) { |
| 541 arithmetic_op(0x03, dst, src); | 545 arithmetic_op(0x03, dst, src); |
| 542 } | 546 } |
| 543 | 547 |
| 544 | |
| 545 void addq(const Operand& dst, Register src) { | 548 void addq(const Operand& dst, Register src) { |
| 546 arithmetic_op(0x01, src, dst); | 549 arithmetic_op(0x01, src, dst); |
| 547 } | 550 } |
| 548 | 551 |
| 549 void addq(Register dst, Immediate src) { | 552 void addq(Register dst, Immediate src) { |
| 550 immediate_arithmetic_op(0x0, dst, src); | 553 immediate_arithmetic_op(0x0, dst, src); |
| 551 } | 554 } |
| 552 | 555 |
| 553 void addq(const Operand& dst, Immediate src) { | 556 void addq(const Operand& dst, Immediate src) { |
| 554 immediate_arithmetic_op(0x0, dst, src); | 557 immediate_arithmetic_op(0x0, dst, src); |
| 555 } | 558 } |
| 556 | 559 |
| 557 void cmpb(Register dst, Immediate src) { | 560 void cmpb(Register dst, Immediate src) { |
| 558 immediate_arithmetic_op_8(0x7, dst, src); | 561 immediate_arithmetic_op_8(0x7, dst, src); |
| 559 } | 562 } |
| 560 | 563 |
| 561 void cmpb(const Operand& dst, Immediate src) { | 564 void cmpb(const Operand& dst, Immediate src) { |
| 562 immediate_arithmetic_op_8(0x7, dst, src); | 565 immediate_arithmetic_op_8(0x7, dst, src); |
| 563 } | 566 } |
| 564 | 567 |
| 565 void cmpl(Register dst, Register src) { | 568 void cmpl(Register dst, Register src) { |
| 566 arithmetic_op_32(0x3B, dst, src); | 569 arithmetic_op_32(0x3B, dst, src); |
| 567 } | 570 } |
| 568 | 571 |
| 569 void cmpl(Register dst, const Operand& src) { | 572 void cmpl(Register dst, const Operand& src) { |
| 570 arithmetic_op_32(0x3B, src, dst); | 573 arithmetic_op_32(0x3B, dst, src); |
| 571 } | 574 } |
| 572 | 575 |
| 573 void cmpl(const Operand& dst, Register src) { | 576 void cmpl(const Operand& dst, Register src) { |
| 574 arithmetic_op_32(0x39, dst, src); | 577 arithmetic_op_32(0x39, src, dst); |
| 575 } | 578 } |
| 576 | 579 |
| 577 void cmpl(Register dst, Immediate src) { | 580 void cmpl(Register dst, Immediate src) { |
| 578 immediate_arithmetic_op_32(0x7, dst, src); | 581 immediate_arithmetic_op_32(0x7, dst, src); |
| 579 } | 582 } |
| 580 | 583 |
| 581 void cmpl(const Operand& dst, Immediate src) { | 584 void cmpl(const Operand& dst, Immediate src) { |
| 582 immediate_arithmetic_op_32(0x7, dst, src); | 585 immediate_arithmetic_op_32(0x7, dst, src); |
| 583 } | 586 } |
| 584 | 587 |
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| 1111 | 1114 |
| 1112 // Emit the code-object-relative offset of the label's position | 1115 // Emit the code-object-relative offset of the label's position |
| 1113 inline void emit_code_relative_offset(Label* label); | 1116 inline void emit_code_relative_offset(Label* label); |
| 1114 | 1117 |
| 1115 // Emit machine code for one of the operations ADD, ADC, SUB, SBC, | 1118 // Emit machine code for one of the operations ADD, ADC, SUB, SBC, |
| 1116 // AND, OR, XOR, or CMP. The encodings of these operations are all | 1119 // AND, OR, XOR, or CMP. The encodings of these operations are all |
| 1117 // similar, differing just in the opcode or in the reg field of the | 1120 // similar, differing just in the opcode or in the reg field of the |
| 1118 // ModR/M byte. | 1121 // ModR/M byte. |
| 1119 void arithmetic_op(byte opcode, Register dst, Register src); | 1122 void arithmetic_op(byte opcode, Register dst, Register src); |
| 1120 void arithmetic_op_32(byte opcode, Register dst, Register src); | 1123 void arithmetic_op_32(byte opcode, Register dst, Register src); |
| 1121 void arithmetic_op_32(byte opcode, const Operand& dst, Register src); | 1124 void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg); |
| 1122 void arithmetic_op(byte opcode, Register reg, const Operand& op); | 1125 void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg); |
| 1123 void immediate_arithmetic_op(byte subcode, Register dst, Immediate src); | 1126 void immediate_arithmetic_op(byte subcode, Register dst, Immediate src); |
| 1124 void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src); | 1127 void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src); |
| 1125 // Operate on a 32-bit word in memory or register. | 1128 // Operate on a 32-bit word in memory or register. |
| 1126 void immediate_arithmetic_op_32(byte subcode, | 1129 void immediate_arithmetic_op_32(byte subcode, |
| 1127 const Operand& dst, | 1130 const Operand& dst, |
| 1128 Immediate src); | 1131 Immediate src); |
| 1129 void immediate_arithmetic_op_32(byte subcode, | 1132 void immediate_arithmetic_op_32(byte subcode, |
| 1130 Register dst, | 1133 Register dst, |
| 1131 Immediate src); | 1134 Immediate src); |
| 1132 // Operate on a byte in memory or register. | 1135 // Operate on a byte in memory or register. |
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| 1203 private: | 1206 private: |
| 1204 Assembler* assembler_; | 1207 Assembler* assembler_; |
| 1205 #ifdef DEBUG | 1208 #ifdef DEBUG |
| 1206 int space_before_; | 1209 int space_before_; |
| 1207 #endif | 1210 #endif |
| 1208 }; | 1211 }; |
| 1209 | 1212 |
| 1210 } } // namespace v8::internal | 1213 } } // namespace v8::internal |
| 1211 | 1214 |
| 1212 #endif // V8_X64_ASSEMBLER_X64_H_ | 1215 #endif // V8_X64_ASSEMBLER_X64_H_ |
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