llvm x86 support

llvm-trunk/lib/Target/X86/X86InstrInfo.cpp

 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the X86 implementation of the TargetInstrInfo class.
@@ skipping 214 matching lines @@
                                                 std::make_pair(RegOp,
                                                               AuxInfo))).second)
       AmbEntries.push_back(MemOp);
   }
 
   // If the third value is 1, then it's folding either a load or a store.
   static const unsigned OpTbl0[][4] = {
     { X86::BT16ri8,     X86::BT16mi8, 1, 0 },
     { X86::BT32ri8,     X86::BT32mi8, 1, 0 },
     { X86::BT64ri8,     X86::BT64mi8, 1, 0 },
-    { X86::CALL32r,     X86::CALL32m, 1, 0 },
+    // @LOCALMOD-START
+    // { X86::CALL32r,     X86::CALL32m, 1, 0 },
+    // @LOCALMOD-END
     { X86::CALL64r,     X86::CALL64m, 1, 0 },
     { X86::CMP16ri,     X86::CMP16mi, 1, 0 },
     { X86::CMP16ri8,    X86::CMP16mi8, 1, 0 },
     { X86::CMP16rr,     X86::CMP16mr, 1, 0 },
     { X86::CMP32ri,     X86::CMP32mi, 1, 0 },
     { X86::CMP32ri8,    X86::CMP32mi8, 1, 0 },
     { X86::CMP32rr,     X86::CMP32mr, 1, 0 },
     { X86::CMP64ri32,   X86::CMP64mi32, 1, 0 },
     { X86::CMP64ri8,    X86::CMP64mi8, 1, 0 },
     { X86::CMP64rr,     X86::CMP64mr, 1, 0 },
     { X86::CMP8ri,      X86::CMP8mi, 1, 0 },
     { X86::CMP8rr,      X86::CMP8mr, 1, 0 },
     { X86::DIV16r,      X86::DIV16m, 1, 0 },
     { X86::DIV32r,      X86::DIV32m, 1, 0 },
     { X86::DIV64r,      X86::DIV64m, 1, 0 },
     { X86::DIV8r,       X86::DIV8m, 1, 0 },
     { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
     { X86::FsMOVAPDrr,  X86::MOVSDmr, 0, 0 },
     { X86::FsMOVAPSrr,  X86::MOVSSmr, 0, 0 },
     { X86::IDIV16r,     X86::IDIV16m, 1, 0 },
     { X86::IDIV32r,     X86::IDIV32m, 1, 0 },
     { X86::IDIV64r,     X86::IDIV64m, 1, 0 },
     { X86::IDIV8r,      X86::IDIV8m, 1, 0 },
     { X86::IMUL16r,     X86::IMUL16m, 1, 0 },
     { X86::IMUL32r,     X86::IMUL32m, 1, 0 },
     { X86::IMUL64r,     X86::IMUL64m, 1, 0 },
     { X86::IMUL8r,      X86::IMUL8m, 1, 0 },
-    { X86::JMP32r,      X86::JMP32m, 1, 0 },
+    // @LOCALMOD-START
+    //{ X86::JMP32r,      X86::JMP32m, 1, 0 },
+    // @LOCALMOD-END
     { X86::JMP64r,      X86::JMP64m, 1, 0 },
     { X86::MOV16ri,     X86::MOV16mi, 0, 0 },
     { X86::MOV16rr,     X86::MOV16mr, 0, 0 },
     { X86::MOV32ri,     X86::MOV32mi, 0, 0 },
     { X86::MOV32rr,     X86::MOV32mr, 0, 0 },
     { X86::MOV32rr_TC,  X86::MOV32mr_TC, 0, 0 },
     { X86::MOV64ri32,   X86::MOV64mi32, 0, 0 },
     { X86::MOV64rr,     X86::MOV64mr, 0, 0 },
     { X86::MOV8ri,      X86::MOV8mi, 0, 0 },
     { X86::MOV8rr,      X86::MOV8mr, 0, 0 },
@@ skipping 3367 matching lines @@
     BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
       .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
                                     X86II::MO_GOT_ABSOLUTE_ADDRESS);
   } else {
     GlobalBaseReg = PC;
   }
 
   X86FI->setGlobalBaseReg(GlobalBaseReg);
   return GlobalBaseReg;
 }