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1 // Copyright 2009 the V8 project authors. All rights reserved. | 1 // Copyright 2009 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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1073 // Handle execution based on instruction types. | 1073 // Handle execution based on instruction types. |
1074 | 1074 |
1075 // Instruction types 0 and 1 are both rolled into one function because they | 1075 // Instruction types 0 and 1 are both rolled into one function because they |
1076 // only differ in the handling of the shifter_operand. | 1076 // only differ in the handling of the shifter_operand. |
1077 void Simulator::DecodeType01(Instr* instr) { | 1077 void Simulator::DecodeType01(Instr* instr) { |
1078 int type = instr->TypeField(); | 1078 int type = instr->TypeField(); |
1079 if ((type == 0) && instr->IsSpecialType0()) { | 1079 if ((type == 0) && instr->IsSpecialType0()) { |
1080 // multiply instruction or extra loads and stores | 1080 // multiply instruction or extra loads and stores |
1081 if (instr->Bits(7, 4) == 9) { | 1081 if (instr->Bits(7, 4) == 9) { |
1082 if (instr->Bit(24) == 0) { | 1082 if (instr->Bit(24) == 0) { |
1083 // multiply instructions | 1083 // Multiply instructions have Rd in a funny place. |
1084 int rd = instr->RdField(); | 1084 int rd = instr->RnField(); |
1085 int rm = instr->RmField(); | 1085 int rm = instr->RmField(); |
1086 int rs = instr->RsField(); | 1086 int rs = instr->RsField(); |
1087 int32_t rs_val = get_register(rs); | 1087 int32_t rs_val = get_register(rs); |
1088 int32_t rm_val = get_register(rm); | 1088 int32_t rm_val = get_register(rm); |
1089 if (instr->Bit(23) == 0) { | 1089 if (instr->Bit(23) == 0) { |
1090 if (instr->Bit(21) == 0) { | 1090 if (instr->Bit(21) == 0) { |
1091 // Format(instr, "mul'cond's 'rd, 'rm, 'rs"); | 1091 // Format(instr, "mul'cond's 'rn, 'rm, 'rs"); |
1092 int32_t alu_out = rm_val * rs_val; | 1092 int32_t alu_out = rm_val * rs_val; |
1093 set_register(rd, alu_out); | 1093 set_register(rd, alu_out); |
1094 if (instr->HasS()) { | 1094 if (instr->HasS()) { |
1095 SetNZFlags(alu_out); | 1095 SetNZFlags(alu_out); |
1096 } | 1096 } |
1097 } else { | 1097 } else { |
1098 Format(instr, "mla'cond's 'rd, 'rm, 'rs, 'rn"); | 1098 UNIMPLEMENTED(); // mla is not used by V8. |
1099 } | 1099 } |
1100 } else { | 1100 } else { |
1101 // Format(instr, "'um'al'cond's 'rn, 'rd, 'rs, 'rm"); | 1101 // Format(instr, "'um'al'cond's 'rn, 'rd, 'rs, 'rm"); |
1102 int rn = instr->RnField(); | 1102 int rd_lo = instr->RdField(); |
1103 int32_t hi_res = 0; | 1103 int32_t hi_res = 0; |
1104 int32_t lo_res = 0; | 1104 int32_t lo_res = 0; |
1105 if (instr->Bit(22) == 0) { | 1105 if (instr->Bit(22) == 1) { |
1106 // signed multiply | 1106 int64_t left_op = static_cast<int32_t>(rm_val); |
1107 UNIMPLEMENTED(); | 1107 int64_t right_op = static_cast<int32_t>(rs_val); |
| 1108 uint64_t result = left_op * right_op; |
| 1109 hi_res = static_cast<int32_t>(result >> 32); |
| 1110 lo_res = static_cast<int32_t>(result & 0xffffffff); |
1108 } else { | 1111 } else { |
1109 // unsigned multiply | 1112 // unsigned multiply |
1110 uint64_t left_op = rm_val; | 1113 uint64_t left_op = static_cast<uint32_t>(rm_val); |
1111 uint64_t right_op = rs_val; | 1114 uint64_t right_op = static_cast<uint32_t>(rs_val); |
1112 uint64_t result = left_op * right_op; | 1115 uint64_t result = left_op * right_op; |
1113 hi_res = static_cast<int32_t>(result >> 32); | 1116 hi_res = static_cast<int32_t>(result >> 32); |
1114 lo_res = static_cast<int32_t>(result & 0xffffffff); | 1117 lo_res = static_cast<int32_t>(result & 0xffffffff); |
1115 } | 1118 } |
1116 set_register(rn, hi_res); | 1119 set_register(rd_lo, lo_res); |
1117 set_register(rd, lo_res); | 1120 set_register(rd, hi_res); |
1118 if (instr->HasS()) { | 1121 if (instr->HasS()) { |
1119 UNIMPLEMENTED(); | 1122 UNIMPLEMENTED(); |
1120 } | 1123 } |
1121 } | 1124 } |
1122 } else { | 1125 } else { |
1123 UNIMPLEMENTED(); // not used by V8 | 1126 UNIMPLEMENTED(); // not used by V8 |
1124 } | 1127 } |
1125 } else { | 1128 } else { |
1126 // extra load/store instructions | 1129 // extra load/store instructions |
1127 int rd = instr->RdField(); | 1130 int rd = instr->RdField(); |
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1791 set_register(r10, r10_val); | 1794 set_register(r10, r10_val); |
1792 set_register(r11, r11_val); | 1795 set_register(r11, r11_val); |
1793 | 1796 |
1794 int result = get_register(r0); | 1797 int result = get_register(r0); |
1795 return reinterpret_cast<Object*>(result); | 1798 return reinterpret_cast<Object*>(result); |
1796 } | 1799 } |
1797 | 1800 |
1798 } } // namespace assembler::arm | 1801 } } // namespace assembler::arm |
1799 | 1802 |
1800 #endif // !defined(__arm__) | 1803 #endif // !defined(__arm__) |
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