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Issue 1523030: Add checks to the ARM simulator to ensure that we flush the icache all... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 8 months ago
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1 // Copyright 2006-2009 the V8 project authors. All rights reserved. 1 // Copyright 2006-2009 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
11 // with the distribution. 11 // with the distribution.
12 // * Neither the name of Google Inc. nor the names of its 12 // * Neither the name of Google Inc. nor the names of its
13 // contributors may be used to endorse or promote products derived 13 // contributors may be used to endorse or promote products derived
14 // from this software without specific prior written permission. 14 // from this software without specific prior written permission.
15 // 15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 27
28 // CPU specific code for arm independent of OS goes here. 28 // CPU specific code for arm independent of OS goes here.
29 #if defined(__arm__) 29 #ifdef __arm__
30 #include <sys/syscall.h> // for cache flushing. 30 #include <sys/syscall.h> // for cache flushing.
31 #endif 31 #endif
32 32
33 #include "v8.h" 33 #include "v8.h"
34 34
35 #include "cpu.h" 35 #include "cpu.h"
36 #include "macro-assembler.h" 36 #include "macro-assembler.h"
37 37
38 #ifndef __arm__
39 #include "simulator-arm.h" // for cache flushing.
40 #endif
41
38 namespace v8 { 42 namespace v8 {
39 namespace internal { 43 namespace internal {
40 44
41 void CPU::Setup() { 45 void CPU::Setup() {
42 CpuFeatures::Probe(); 46 CpuFeatures::Probe();
43 } 47 }
44 48
45 49
46 void CPU::FlushICache(void* start, size_t size) { 50 void CPU::FlushICache(void* start, size_t size) {
47 #if !defined (__arm__) 51 #if !defined (__arm__)
48 // Not generating ARM instructions for C-code. This means that we are 52 // Not generating ARM instructions for C-code. This means that we are
49 // building an ARM emulator based target. No I$ flushes are necessary. 53 // building an ARM emulator based target. We should notify the simulator
54 // that the Icache was flushed.
50 // None of this code ends up in the snapshot so there are no issues 55 // None of this code ends up in the snapshot so there are no issues
51 // around whether or not to generate the code when building snapshots. 56 // around whether or not to generate the code when building snapshots.
57 assembler::arm::Simulator::FlushICache(start, size);
52 #else 58 #else
53 // Ideally, we would call 59 // Ideally, we would call
54 // syscall(__ARM_NR_cacheflush, start, 60 // syscall(__ARM_NR_cacheflush, start,
55 // reinterpret_cast<intptr_t>(start) + size, 0); 61 // reinterpret_cast<intptr_t>(start) + size, 0);
56 // however, syscall(int, ...) is not supported on all platforms, especially 62 // however, syscall(int, ...) is not supported on all platforms, especially
57 // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly. 63 // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
58 64
59 register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start); 65 register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
60 register uint32_t end asm("a2") = 66 register uint32_t end asm("a2") =
61 reinterpret_cast<uint32_t>(start) + size; 67 reinterpret_cast<uint32_t>(start) + size;
(...skipping 61 matching lines...) Expand 10 before | Expand all | Expand 10 after
123 129
124 void CPU::DebugBreak() { 130 void CPU::DebugBreak() {
125 #if !defined (__arm__) || !defined(CAN_USE_ARMV5_INSTRUCTIONS) 131 #if !defined (__arm__) || !defined(CAN_USE_ARMV5_INSTRUCTIONS)
126 UNIMPLEMENTED(); // when building ARM emulator target 132 UNIMPLEMENTED(); // when building ARM emulator target
127 #else 133 #else
128 asm volatile("bkpt 0"); 134 asm volatile("bkpt 0");
129 #endif 135 #endif
130 } 136 }
131 137
132 } } // namespace v8::internal 138 } } // namespace v8::internal
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