| Index: src/arm/disasm-arm.cc
|
| ===================================================================
|
| --- src/arm/disasm-arm.cc (revision 2306)
|
| +++ src/arm/disasm-arm.cc (working copy)
|
| @@ -593,7 +593,17 @@
|
| if (instr->HasS()) {
|
| Format(instr, "teq'cond 'rn, 'shift_op");
|
| } else {
|
| - Unknown(instr); // not used by V8
|
| + switch (instr->Bits(7, 4)) {
|
| + case BX:
|
| + Format(instr, "bx'cond 'rm");
|
| + break;
|
| + case BLX:
|
| + Format(instr, "blx'cond 'rm");
|
| + break;
|
| + default:
|
| + Unknown(instr); // not used by V8
|
| + break;
|
| + }
|
| }
|
| break;
|
| }
|
| @@ -609,7 +619,14 @@
|
| if (instr->HasS()) {
|
| Format(instr, "cmn'cond 'rn, 'shift_op");
|
| } else {
|
| - Unknown(instr); // not used by V8
|
| + switch (instr->Bits(7, 4)) {
|
| + case CLZ:
|
| + Format(instr, "clz'cond 'rd, 'rm");
|
| + break;
|
| + default:
|
| + Unknown(instr); // not used by V8
|
| + break;
|
| + }
|
| }
|
| break;
|
| }
|
|
|