More changes to make the simulator run code that for the ARM5 snapshot.

src/arm/simulator-arm.cc

 // Copyright 2009 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1342 matching lines @@
       }
 
       case TEQ: {
         if (instr->HasS()) {
           // Format(instr, "teq'cond 'rn, 'shift_rm");
           // Format(instr, "teq'cond 'rn, 'imm");
           alu_out = rn_val ^ shifter_operand;
           SetNZFlags(alu_out);
           SetCFlag(shifter_carry_out);
         } else {
-          UNIMPLEMENTED();
+          ASSERT(type == 0);
+          int rm = instr->RmField();
+          switch (instr->Bits(7, 4)) {
+            case BX:
+              set_pc(get_register(rm));
+              break;
+            case BLX: {
+              uint32_t old_pc = get_pc();
+              set_pc(get_register(rm));
+              set_register(lr, old_pc + Instr::kInstrSize);
+              break;
+            }
+            default:
+              UNIMPLEMENTED();
+          }
         }
         break;
       }
 
       case CMP: {
         if (instr->HasS()) {
           // Format(instr, "cmp'cond 'rn, 'shift_rm");
           // Format(instr, "cmp'cond 'rn, 'imm");
           alu_out = rn_val - shifter_operand;
           SetNZFlags(alu_out);
           SetCFlag(!BorrowFrom(rn_val, shifter_operand));
           SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
         } else {
           UNIMPLEMENTED();
         }
         break;
       }
 
       case CMN: {
         if (instr->HasS()) {
           Format(instr, "cmn'cond 'rn, 'shift_rm");
           Format(instr, "cmn'cond 'rn, 'imm");
         } else {
-          UNIMPLEMENTED();
+          ASSERT(type == 0);
+          int rm = instr->RmField();
+          int rd = instr->RdField();
+          switch (instr->Bits(7, 4)) {
+            case CLZ: {
+              uint32_t bits = get_register(rm);
+              int leading_zeros = 0;
+              if (bits == 0) {
+                leading_zeros = 32;
+              } else {
+                while ((bits & 0x80000000u) == 0) {
+                  bits <<= 1;
+                  leading_zeros++;
+                }
+              }
+              set_register(rd, leading_zeros);
+              break;
+            }
+            default:
+              UNIMPLEMENTED();
+          }
         }
         break;
       }
 
       case ORR: {
         // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
         // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
         alu_out = rn_val | shifter_operand;
         set_register(rd, alu_out);
         if (instr->HasS()) {
@@ skipping 359 matching lines @@
   set_register(r10, r10_val);
   set_register(r11, r11_val);
 
   int result = get_register(r0);
   return reinterpret_cast<Object*>(result);
 }
 
 } }  // namespace assembler::arm
 
 #endif  // !defined(__arm__)