More changes to make the simulator run code that for the ARM5 snapshot.

src/arm/constants-arm.h

 // Copyright 2009 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 18 matching lines @@
 #define V8_ARM_CONSTANTS_ARM_H_
 
 // The simulator emulates the EABI so we define the USE_ARM_EABI macro if we
 // are not running on real ARM hardware.  One reason for this is that the
 // old ABI uses fp registers in the calling convention and the simulator does
 // not simulate fp registers or coroutine instructions.
 #if defined(__ARM_EABI__) || !defined(__arm__)
 # define USE_ARM_EABI 1
 #endif
 
+// This means that interwork-compatible jump instructions are generated.  We
+// want to generate them on the simulator too so it makes snapshots that can
+// be used on real hardware.
+#if defined(__THUMB_INTERWORK__) || !defined(__arm__)
+# define USE_THUMB_INTERWORK 1
+#endif
+
+// Simulator should support ARM5 instructions.
+#if !defined(__arm__)
+# define __ARM_ARCH_5__ 1
+# define __ARM_ARCH_5T__ 1
+#endif
+
 namespace assembler {
 namespace arm {
 
 // Defines constants and accessor classes to assemble, disassemble and
 // simulate ARM instructions.
 //
 // Section references in the code refer to the "ARM Architecture Reference
 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
 //
 // Constants for specific fields are defined in their respective named enums.
@@ skipping 41 matching lines @@
   CMP = 10,  // Compare
   CMN = 11,  // Compare Negated
   ORR = 12,  // Logical (inclusive) OR
   MOV = 13,  // Move
   BIC = 14,  // Bit Clear
   MVN = 15,  // Move Not
   max_operand = 16
 };
 
 
+// Some special instructions encoded as a TEQ with S=0 (bit 20).
+enum Opcode9Bits {
+  BX   =  1,
+  BXJ  =  2,
+  BLX  =  3,
+  BKPT =  7
+};
+
+
+// Some special instructions encoded as a CMN with S=0 (bit 20).
+enum Opcode11Bits {
+  CLZ  =  1
+};
+
+
+// S
+
+
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 enum Shift {
   no_shift = -1,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
   ASR = 2,  // Arithmetic shift right
   ROR = 3,  // Rotate right
   max_shift = 4
 };
 
@@ skipping 124 matching lines @@
 
  private:
   // We need to prevent the creation of instances of class Instr.
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 
 } }  // namespace assembler::arm
 
 #endif  // V8_ARM_CONSTANTS_ARM_H_