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1 // Copyright 2009 the V8 project authors. All rights reserved. | 1 // Copyright 2009 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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29 #define V8_ARM_CONSTANTS_ARM_H_ | 29 #define V8_ARM_CONSTANTS_ARM_H_ |
30 | 30 |
31 // The simulator emulates the EABI so we define the USE_ARM_EABI macro if we | 31 // The simulator emulates the EABI so we define the USE_ARM_EABI macro if we |
32 // are not running on real ARM hardware. One reason for this is that the | 32 // are not running on real ARM hardware. One reason for this is that the |
33 // old ABI uses fp registers in the calling convention and the simulator does | 33 // old ABI uses fp registers in the calling convention and the simulator does |
34 // not simulate fp registers or coroutine instructions. | 34 // not simulate fp registers or coroutine instructions. |
35 #if defined(__ARM_EABI__) || !defined(__arm__) | 35 #if defined(__ARM_EABI__) || !defined(__arm__) |
36 # define USE_ARM_EABI 1 | 36 # define USE_ARM_EABI 1 |
37 #endif | 37 #endif |
38 | 38 |
| 39 // This means that interwork-compatible jump instructions are generated. We |
| 40 // want to generate them on the simulator too so it makes snapshots that can |
| 41 // be used on real hardware. |
| 42 #if defined(__THUMB_INTERWORK__) || !defined(__arm__) |
| 43 # define USE_THUMB_INTERWORK 1 |
| 44 #endif |
| 45 |
| 46 // Simulator should support ARM5 instructions. |
| 47 #if !defined(__arm__) |
| 48 # define __ARM_ARCH_5__ 1 |
| 49 # define __ARM_ARCH_5T__ 1 |
| 50 #endif |
| 51 |
39 namespace assembler { | 52 namespace assembler { |
40 namespace arm { | 53 namespace arm { |
41 | 54 |
42 // Defines constants and accessor classes to assemble, disassemble and | 55 // Defines constants and accessor classes to assemble, disassemble and |
43 // simulate ARM instructions. | 56 // simulate ARM instructions. |
44 // | 57 // |
45 // Section references in the code refer to the "ARM Architecture Reference | 58 // Section references in the code refer to the "ARM Architecture Reference |
46 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) | 59 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) |
47 // | 60 // |
48 // Constants for specific fields are defined in their respective named enums. | 61 // Constants for specific fields are defined in their respective named enums. |
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90 CMP = 10, // Compare | 103 CMP = 10, // Compare |
91 CMN = 11, // Compare Negated | 104 CMN = 11, // Compare Negated |
92 ORR = 12, // Logical (inclusive) OR | 105 ORR = 12, // Logical (inclusive) OR |
93 MOV = 13, // Move | 106 MOV = 13, // Move |
94 BIC = 14, // Bit Clear | 107 BIC = 14, // Bit Clear |
95 MVN = 15, // Move Not | 108 MVN = 15, // Move Not |
96 max_operand = 16 | 109 max_operand = 16 |
97 }; | 110 }; |
98 | 111 |
99 | 112 |
| 113 // Some special instructions encoded as a TEQ with S=0 (bit 20). |
| 114 enum Opcode9Bits { |
| 115 BX = 1, |
| 116 BXJ = 2, |
| 117 BLX = 3, |
| 118 BKPT = 7 |
| 119 }; |
| 120 |
| 121 |
| 122 // Some special instructions encoded as a CMN with S=0 (bit 20). |
| 123 enum Opcode11Bits { |
| 124 CLZ = 1 |
| 125 }; |
| 126 |
| 127 |
| 128 // S |
| 129 |
| 130 |
100 // Shifter types for Data-processing operands as defined in section A5.1.2. | 131 // Shifter types for Data-processing operands as defined in section A5.1.2. |
101 enum Shift { | 132 enum Shift { |
102 no_shift = -1, | 133 no_shift = -1, |
103 LSL = 0, // Logical shift left | 134 LSL = 0, // Logical shift left |
104 LSR = 1, // Logical shift right | 135 LSR = 1, // Logical shift right |
105 ASR = 2, // Arithmetic shift right | 136 ASR = 2, // Arithmetic shift right |
106 ROR = 3, // Rotate right | 137 ROR = 3, // Rotate right |
107 max_shift = 4 | 138 max_shift = 4 |
108 }; | 139 }; |
109 | 140 |
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234 | 265 |
235 private: | 266 private: |
236 // We need to prevent the creation of instances of class Instr. | 267 // We need to prevent the creation of instances of class Instr. |
237 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 268 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
238 }; | 269 }; |
239 | 270 |
240 | 271 |
241 } } // namespace assembler::arm | 272 } } // namespace assembler::arm |
242 | 273 |
243 #endif // V8_ARM_CONSTANTS_ARM_H_ | 274 #endif // V8_ARM_CONSTANTS_ARM_H_ |
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