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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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809 | 809 |
810 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) { | 810 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) { |
811 addrmod1(cond | 15*B21 | s, r0, dst, src); | 811 addrmod1(cond | 15*B21 | s, r0, dst, src); |
812 } | 812 } |
813 | 813 |
814 | 814 |
815 // Multiply instructions | 815 // Multiply instructions |
816 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, | 816 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, |
817 SBit s, Condition cond) { | 817 SBit s, Condition cond) { |
818 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); | 818 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
819 ASSERT(!dst.is(src1)); | |
820 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | | 819 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | |
821 src2.code()*B8 | B7 | B4 | src1.code()); | 820 src2.code()*B8 | B7 | B4 | src1.code()); |
822 } | 821 } |
823 | 822 |
824 | 823 |
825 void Assembler::mul(Register dst, Register src1, Register src2, | 824 void Assembler::mul(Register dst, Register src1, Register src2, |
826 SBit s, Condition cond) { | 825 SBit s, Condition cond) { |
827 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | 826 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
828 ASSERT(!dst.is(src1)); | |
829 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); | 827 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
830 } | 828 } |
831 | 829 |
832 | 830 |
833 void Assembler::smlal(Register dstL, | 831 void Assembler::smlal(Register dstL, |
834 Register dstH, | 832 Register dstH, |
835 Register src1, | 833 Register src1, |
836 Register src2, | 834 Register src2, |
837 SBit s, | 835 SBit s, |
838 Condition cond) { | 836 Condition cond) { |
839 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | 837 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
840 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | 838 ASSERT(!dstL.is(dstH)); |
841 emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 | | 839 emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
842 src2.code()*B8 | B7 | B4 | src1.code()); | 840 src2.code()*B8 | B7 | B4 | src1.code()); |
843 } | 841 } |
844 | 842 |
845 | 843 |
846 void Assembler::smull(Register dstL, | 844 void Assembler::smull(Register dstL, |
847 Register dstH, | 845 Register dstH, |
848 Register src1, | 846 Register src1, |
849 Register src2, | 847 Register src2, |
850 SBit s, | 848 SBit s, |
851 Condition cond) { | 849 Condition cond) { |
852 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | 850 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
853 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | 851 ASSERT(!dstL.is(dstH)); |
854 emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | | 852 emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | |
855 src2.code()*B8 | B7 | B4 | src1.code()); | 853 src2.code()*B8 | B7 | B4 | src1.code()); |
856 } | 854 } |
857 | 855 |
858 | 856 |
859 void Assembler::umlal(Register dstL, | 857 void Assembler::umlal(Register dstL, |
860 Register dstH, | 858 Register dstH, |
861 Register src1, | 859 Register src1, |
862 Register src2, | 860 Register src2, |
863 SBit s, | 861 SBit s, |
864 Condition cond) { | 862 Condition cond) { |
865 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | 863 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
866 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | 864 ASSERT(!dstL.is(dstH)); |
867 emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 | | 865 emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
868 src2.code()*B8 | B7 | B4 | src1.code()); | 866 src2.code()*B8 | B7 | B4 | src1.code()); |
869 } | 867 } |
870 | 868 |
871 | 869 |
872 void Assembler::umull(Register dstL, | 870 void Assembler::umull(Register dstL, |
873 Register dstH, | 871 Register dstH, |
874 Register src1, | 872 Register src1, |
875 Register src2, | 873 Register src2, |
876 SBit s, | 874 SBit s, |
877 Condition cond) { | 875 Condition cond) { |
878 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); | 876 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
879 ASSERT(!dstL.is(dstH) && !dstH.is(src1) && !src1.is(dstL)); | 877 ASSERT(!dstL.is(dstH)); |
880 emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 | | 878 emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | |
881 src2.code()*B8 | B7 | B4 | src1.code()); | 879 src2.code()*B8 | B7 | B4 | src1.code()); |
882 } | 880 } |
883 | 881 |
884 | 882 |
885 // Miscellaneous arithmetic instructions | 883 // Miscellaneous arithmetic instructions |
886 void Assembler::clz(Register dst, Register src, Condition cond) { | 884 void Assembler::clz(Register dst, Register src, Condition cond) { |
887 // v5 and above. | 885 // v5 and above. |
888 ASSERT(!dst.is(pc) && !src.is(pc)); | 886 ASSERT(!dst.is(pc) && !src.is(pc)); |
889 emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 | | 887 emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 | |
890 15*B8 | B4 | src.code()); | 888 15*B8 | B4 | src.code()); |
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1465 bind(&after_pool); | 1463 bind(&after_pool); |
1466 } | 1464 } |
1467 | 1465 |
1468 // Since a constant pool was just emitted, move the check offset forward by | 1466 // Since a constant pool was just emitted, move the check offset forward by |
1469 // the standard interval. | 1467 // the standard interval. |
1470 next_buffer_check_ = pc_offset() + kCheckConstInterval; | 1468 next_buffer_check_ = pc_offset() + kCheckConstInterval; |
1471 } | 1469 } |
1472 | 1470 |
1473 | 1471 |
1474 } } // namespace v8::internal | 1472 } } // namespace v8::internal |
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