Index: src/x64/assembler-x64-inl.h |
diff --git a/src/x64/assembler-x64-inl.h b/src/x64/assembler-x64-inl.h |
index bcdf3f4d622260d5793c167b91de8026fad9d57e..196f2eedbd474cf855b7a1ecef304e5b6f9c0ff6 100644 |
--- a/src/x64/assembler-x64-inl.h |
+++ b/src/x64/assembler-x64-inl.h |
@@ -29,6 +29,7 @@ |
#define V8_X64_ASSEMBLER_X64_INL_H_ |
#include "cpu.h" |
+#include "memory.h" |
namespace v8 { |
namespace internal { |
@@ -74,11 +75,21 @@ void Assembler::emit_rex_64(Register reg, Register rm_reg) { |
} |
+void Assembler::emit_rex_64(XMMRegister reg, Register rm_reg) { |
+ emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3); |
+} |
+ |
+ |
void Assembler::emit_rex_64(Register reg, const Operand& op) { |
emit(0x48 | reg.high_bit() << 2 | op.rex_); |
} |
+void Assembler::emit_rex_64(XMMRegister reg, const Operand& op) { |
+ emit(0x48 | (reg.code() & 0x8) >> 1 | op.rex_); |
+} |
+ |
+ |
void Assembler::emit_rex_64(Register rm_reg) { |
ASSERT_EQ(rm_reg.code() & 0xf, rm_reg.code()); |
emit(0x48 | rm_reg.high_bit()); |
@@ -122,6 +133,24 @@ void Assembler::emit_optional_rex_32(Register reg, const Operand& op) { |
} |
+void Assembler::emit_optional_rex_32(XMMRegister reg, const Operand& op) { |
+ byte rex_bits = (reg.code() & 0x8) >> 1 | op.rex_; |
+ if (rex_bits != 0) emit(0x40 | rex_bits); |
+} |
+ |
+ |
+void Assembler::emit_optional_rex_32(XMMRegister reg, XMMRegister base) { |
+ byte rex_bits = (reg.code() & 0x8) >> 1 | (base.code() & 0x8) >> 3; |
+ if (rex_bits != 0) emit(0x40 | rex_bits); |
+} |
+ |
+ |
+void Assembler::emit_optional_rex_32(XMMRegister reg, Register base) { |
+ byte rex_bits = (reg.code() & 0x8) >> 1 | (base.code() & 0x8) >> 3; |
+ if (rex_bits != 0) emit(0x40 | rex_bits); |
+} |
+ |
+ |
void Assembler::emit_optional_rex_32(Register rm_reg) { |
if (rm_reg.high_bit()) emit(0x41); |
} |