X64: Addition binary operation.

src/x64/assembler-x64.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 138 matching lines @@
 extern MMXRegister mm9;
 extern MMXRegister mm10;
 extern MMXRegister mm11;
 extern MMXRegister mm12;
 extern MMXRegister mm13;
 extern MMXRegister mm14;
 extern MMXRegister mm15;
 
 
 struct XMMRegister {
-  bool is_valid() const  { return 0 <= code_ && code_ < 2; }
+  bool is_valid() const  { return 0 <= code_ && code_ < 16; }
   int code() const  {
     ASSERT(is_valid());
     return code_;
   }
 
   int code_;
 };
 
 extern XMMRegister xmm0;
 extern XMMRegister xmm1;
@@ skipping 153 matching lines @@
   inline void set_disp8(int disp);
   inline void set_disp32(int disp);
 
   friend class Assembler;
 };
 
 
 // CpuFeatures keeps track of which features are supported by the target CPU.
 // Supported features must be enabled by a Scope before use.
 // Example:
-//   if (CpuFeatures::IsSupported(SSE2)) {
-//     CpuFeatures::Scope fscope(SSE2);
-//     // Generate SSE2 floating point code.
+//   if (CpuFeatures::IsSupported(SSE3)) {
+//     CpuFeatures::Scope fscope(SSE3);
+//     // Generate SSE3 floating point code.
 //   } else {
-//     // Generate standard x87 floating point code.
+//     // Generate standard x87 or SSE2 floating point code.
 //   }
 class CpuFeatures : public AllStatic {
  public:
   // Feature flags bit positions. They are mostly based on the CPUID spec.
   // (We assign CPUID itself to one of the currently reserved bits --
   // feel free to change this if needed.)
   enum Feature { SSE3 = 32, SSE2 = 26, CMOV = 15, RDTSC = 4, CPUID = 10 };
   // Detect features of the target CPU. Set safe defaults if the serializer
   // is enabled (snapshots must be portable).
   static void Probe();
@@ skipping 16 matching lines @@
     }
     ~Scope() { CpuFeatures::enabled_ = old_enabled_; }
    private:
     uint64_t old_enabled_;
 #else
    public:
     explicit Scope(Feature f) {}
 #endif
   };
  private:
+  // Safe defaults include SSE2 and CMOV for X64. It is always available, if
+  // anyone checks, but they shouldn't need to check.
+  static const uint64_t kDefaultCpuFeatures =
+      (1 << CpuFeatures::SSE2 | 1 << CpuFeatures::CMOV);
   static uint64_t supported_;
   static uint64_t enabled_;
 };
 
 
 class Assembler : public Malloced {
  private:
   // We check before assembling an instruction that there is sufficient
   // space to write an instruction and its relocation information.
   // The relocation writer's position must be kGap bytes above the end of
@@ skipping 106 matching lines @@
   void movq(Register dst, ExternalReference ext);
   void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode);
 
   void movsxlq(Register dst, Register src);
   void movzxbq(Register dst, const Operand& src);
 
   // New x64 instruction to load from an immediate 64-bit pointer into RAX.
   void load_rax(void* ptr, RelocInfo::Mode rmode);
   void load_rax(ExternalReference ext);
 
-  // Conditional moves
-  // Implement conditional moves here.
+  // Conditional moves.
+  void cmovq(Condition cc, Register dst, Register src);
+  void cmovq(Condition cc, Register dst, const Operand& src);
+  void cmovl(Condition cc, Register dst, Register src);
+  void cmovl(Condition cc, Register dst, const Operand& src);
 
   // Exchange two registers
   void xchg(Register dst, Register src);
 
   // Arithmetics
   void addq(Register dst, Register src) {
     arithmetic_op(0x03, dst, src);
   }
 
   void addl(Register dst, Register src) {
     arithmetic_op_32(0x03, dst, src);
   }
 
+  void addl(Register dst, Immediate src) {
+    immediate_arithmetic_op_32(0x0, dst, src);
+  }
+
   void addq(Register dst, const Operand& src) {
     arithmetic_op(0x03, dst, src);
   }
 
 
   void addq(const Operand& dst, Register src) {
     arithmetic_op(0x01, src, dst);
   }
 
   void addq(Register dst, Immediate src) {
@@ skipping 312 matching lines @@
   void fcompp();
   void fnstsw_ax();
   void fwait();
   void fnclex();
 
   void fsin();
   void fcos();
 
   void frndint();
 
-    // SSE2 instructions
+  void sahf();
+
+  // SSE2 instructions
+  void movsd(const Operand& dst, XMMRegister src);
+  void movsd(Register src, XMMRegister dst);
+  void movsd(XMMRegister dst, Register src);
+  void movsd(XMMRegister src, const Operand& dst);
+
   void cvttss2si(Register dst, const Operand& src);
   void cvttsd2si(Register dst, const Operand& src);
 
-  void cvtsi2sd(XMMRegister dst, const Operand& src);
+  void cvtlsi2sd(XMMRegister dst, const Operand& src);
+  void cvtlsi2sd(XMMRegister dst, Register src);
+  void cvtqsi2sd(XMMRegister dst, const Operand& src);
+  void cvtqsi2sd(XMMRegister dst, Register src);
 
   void addsd(XMMRegister dst, XMMRegister src);
   void subsd(XMMRegister dst, XMMRegister src);
   void mulsd(XMMRegister dst, XMMRegister src);
   void divsd(XMMRegister dst, XMMRegister src);
 
+
+  void emit_sse_operand(XMMRegister dst, XMMRegister src);
+  void emit_sse_operand(XMMRegister reg, const Operand& adr);
+  void emit_sse_operand(XMMRegister dst, Register src);
+
   // Use either movsd or movlpd.
   // void movdbl(XMMRegister dst, const Operand& src);
   // void movdbl(const Operand& dst, XMMRegister src);
 
   // Debugging
   void Print();
 
   // Check the code size generated from label to here.
   int SizeOfCodeGeneratedSince(Label* l) { return pc_offset() - l->pos(); }
 
@@ skipping 58 matching lines @@
   inline void emit(Handle<Object> handle);
   inline void emitq(uint64_t x, RelocInfo::Mode rmode);
   inline void emitw(uint16_t x);
   void emit(Immediate x) { emitl(x.value_); }
 
   // Emits a REX prefix that encodes a 64-bit operand size and
   // the top bit of both register codes.
   // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
   // REX.W is set.
   inline void emit_rex_64(Register reg, Register rm_reg);
+  inline void emit_rex_64(XMMRegister reg, Register rm_reg);
 
   // Emits a REX prefix that encodes a 64-bit operand size and
   // the top bit of the destination, index, and base register codes.
   // The high bit of reg is used for REX.R, the high bit of op's base
   // register is used for REX.B, and the high bit of op's index register
   // is used for REX.X.  REX.W is set.
   inline void emit_rex_64(Register reg, const Operand& op);
+  inline void emit_rex_64(XMMRegister reg, const Operand& op);
 
   // Emits a REX prefix that encodes a 64-bit operand size and
   // the top bit of the register code.
   // The high bit of register is used for REX.B.
   // REX.W is set and REX.R and REX.X are clear.
   inline void emit_rex_64(Register rm_reg);
 
   // Emits a REX prefix that encodes a 64-bit operand size and
   // the top bit of the index and base register codes.
   // The high bit of op's base register is used for REX.B, and the high
@@ skipping 24 matching lines @@
   // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
   // REX.W is cleared.  If no REX bits are set, no byte is emitted.
   inline void emit_optional_rex_32(Register reg, Register rm_reg);
 
   // The high bit of reg is used for REX.R, the high bit of op's base
   // register is used for REX.B, and the high bit of op's index register
   // is used for REX.X.  REX.W is cleared.  If no REX bits are set, nothing
   // is emitted.
   inline void emit_optional_rex_32(Register reg, const Operand& op);
 
+  // As for emit_optional_rex_32(Register, Register), except that
+  // the registers are XMM registers.
+  inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
+
+  // As for emit_optional_rex_32(Register, Register), except that
+  // the registers are XMM registers.
+  inline void emit_optional_rex_32(XMMRegister reg, Register base);
+
+  // As for emit_optional_rex_32(Register, const Operand&), except that
+  // the register is an XMM register.
+  inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
+
   // Optionally do as emit_rex_32(Register) if the register number has
   // the high bit set.
   inline void emit_optional_rex_32(Register rm_reg);
 
   // Optionally do as emit_rex_32(const Operand&) if the operand register
   // numbers have a high bit set.
   inline void emit_optional_rex_32(const Operand& op);
 
 
   // Emit the ModR/M byte, and optionally the SIB byte and
@@ skipping 110 matching lines @@
  private:
   Assembler* assembler_;
 #ifdef DEBUG
   int space_before_;
 #endif
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_X64_ASSEMBLER_X64_H_