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| 1 // Copyright 2009 the V8 project authors. All rights reserved. | 1 // Copyright 2009 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 63 } | 63 } |
| 64 | 64 |
| 65 | 65 |
| 66 void Assembler::emitw(uint16_t x) { | 66 void Assembler::emitw(uint16_t x) { |
| 67 Memory::uint16_at(pc_) = x; | 67 Memory::uint16_at(pc_) = x; |
| 68 pc_ += sizeof(uint16_t); | 68 pc_ += sizeof(uint16_t); |
| 69 } | 69 } |
| 70 | 70 |
| 71 | 71 |
| 72 void Assembler::emit_rex_64(Register reg, Register rm_reg) { | 72 void Assembler::emit_rex_64(Register reg, Register rm_reg) { |
| 73 emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3); | 73 emit(0x48 | reg.high_bit() << 2 | rm_reg.high_bit()); |
| 74 } | 74 } |
| 75 | 75 |
| 76 | 76 |
| 77 void Assembler::emit_rex_64(Register reg, const Operand& op) { | 77 void Assembler::emit_rex_64(Register reg, const Operand& op) { |
| 78 emit(0x48 | (reg.code() & 0x8) >> 1 | op.rex_); | 78 emit(0x48 | reg.high_bit() << 2 | op.rex_); |
| 79 } | 79 } |
| 80 | 80 |
| 81 | 81 |
| 82 void Assembler::emit_rex_64(Register rm_reg) { | 82 void Assembler::emit_rex_64(Register rm_reg) { |
| 83 ASSERT_EQ(rm_reg.code() & 0xf, rm_reg.code()); | 83 ASSERT_EQ(rm_reg.code() & 0xf, rm_reg.code()); |
| 84 emit(0x48 | (rm_reg.code() >> 3)); | 84 emit(0x48 | rm_reg.high_bit()); |
| 85 } | 85 } |
| 86 | 86 |
| 87 | 87 |
| 88 void Assembler::emit_rex_64(const Operand& op) { | 88 void Assembler::emit_rex_64(const Operand& op) { |
| 89 emit(0x48 | op.rex_); | 89 emit(0x48 | op.rex_); |
| 90 } | 90 } |
| 91 | 91 |
| 92 | 92 |
| 93 void Assembler::emit_rex_32(Register reg, Register rm_reg) { | 93 void Assembler::emit_rex_32(Register reg, Register rm_reg) { |
| 94 emit(0x40 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3); | 94 emit(0x40 | reg.high_bit() << 2 | rm_reg.high_bit()); |
| 95 } | 95 } |
| 96 | 96 |
| 97 | 97 |
| 98 void Assembler::emit_rex_32(Register reg, const Operand& op) { | 98 void Assembler::emit_rex_32(Register reg, const Operand& op) { |
| 99 emit(0x40 | (reg.code() & 0x8) >> 1 | op.rex_); | 99 emit(0x40 | reg.high_bit() << 2 | op.rex_); |
| 100 } | 100 } |
| 101 | 101 |
| 102 | 102 |
| 103 void Assembler::emit_rex_32(Register rm_reg) { | 103 void Assembler::emit_rex_32(Register rm_reg) { |
| 104 emit(0x40 | (rm_reg.code() & 0x8) >> 3); | 104 emit(0x40 | rm_reg.high_bit()); |
| 105 } | 105 } |
| 106 | 106 |
| 107 | 107 |
| 108 void Assembler::emit_rex_32(const Operand& op) { | 108 void Assembler::emit_rex_32(const Operand& op) { |
| 109 emit(0x40 | op.rex_); | 109 emit(0x40 | op.rex_); |
| 110 } | 110 } |
| 111 | 111 |
| 112 | 112 |
| 113 void Assembler::emit_optional_rex_32(Register reg, Register rm_reg) { | 113 void Assembler::emit_optional_rex_32(Register reg, Register rm_reg) { |
| 114 byte rex_bits = (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3; | 114 byte rex_bits = reg.high_bit() << 2 | rm_reg.high_bit(); |
| 115 if (rex_bits != 0) emit(0x40 | rex_bits); | 115 if (rex_bits != 0) emit(0x40 | rex_bits); |
| 116 } | 116 } |
| 117 | 117 |
| 118 | 118 |
| 119 void Assembler::emit_optional_rex_32(Register reg, const Operand& op) { | 119 void Assembler::emit_optional_rex_32(Register reg, const Operand& op) { |
| 120 byte rex_bits = (reg.code() & 0x8) >> 1 | op.rex_; | 120 byte rex_bits = reg.high_bit() << 2 | op.rex_; |
| 121 if (rex_bits != 0) emit(0x40 | rex_bits); | 121 if (rex_bits != 0) emit(0x40 | rex_bits); |
| 122 } | 122 } |
| 123 | 123 |
| 124 | 124 |
| 125 void Assembler::emit_optional_rex_32(Register rm_reg) { | 125 void Assembler::emit_optional_rex_32(Register rm_reg) { |
| 126 if (rm_reg.code() > 0x7) emit(0x41); | 126 if (rm_reg.high_bit()) emit(0x41); |
| 127 } | 127 } |
| 128 | 128 |
| 129 | 129 |
| 130 void Assembler::emit_optional_rex_32(const Operand& op) { | 130 void Assembler::emit_optional_rex_32(const Operand& op) { |
| 131 if (op.rex_ != 0) emit(0x40 | op.rex_); | 131 if (op.rex_ != 0) emit(0x40 | op.rex_); |
| 132 } | 132 } |
| 133 | 133 |
| 134 | 134 |
| 135 Address Assembler::target_address_at(Address pc) { | 135 Address Assembler::target_address_at(Address pc) { |
| 136 return Memory::Address_at(pc); | 136 return Memory::Address_at(pc); |
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| 237 | 237 |
| 238 Object** RelocInfo::call_object_address() { | 238 Object** RelocInfo::call_object_address() { |
| 239 UNIMPLEMENTED(); // IA32 code below. | 239 UNIMPLEMENTED(); // IA32 code below. |
| 240 ASSERT(IsCallInstruction()); | 240 ASSERT(IsCallInstruction()); |
| 241 return reinterpret_cast<Object**>(pc_ + 1); | 241 return reinterpret_cast<Object**>(pc_ + 1); |
| 242 } | 242 } |
| 243 | 243 |
| 244 // ----------------------------------------------------------------------------- | 244 // ----------------------------------------------------------------------------- |
| 245 // Implementation of Operand | 245 // Implementation of Operand |
| 246 | 246 |
| 247 void Operand::set_modrm(int mod, Register rm) { | 247 void Operand::set_modrm(int mod, Register rm_reg) { |
| 248 ASSERT((mod & -4) == 0); | 248 ASSERT(is_uint2(mod)); |
| 249 buf_[0] = (mod << 6) | (rm.code() & 0x7); | 249 buf_[0] = mod << 6 | rm_reg.low_bits(); |
| 250 // Set REX.B to the high bit of rm.code(). | 250 // Set REX.B to the high bit of rm.code(). |
| 251 rex_ |= (rm.code() >> 3); | 251 rex_ |= rm_reg.high_bit(); |
| 252 } | 252 } |
| 253 | 253 |
| 254 | 254 |
| 255 void Operand::set_sib(ScaleFactor scale, Register index, Register base) { | 255 void Operand::set_sib(ScaleFactor scale, Register index, Register base) { |
| 256 ASSERT(len_ == 1); | 256 ASSERT(len_ == 1); |
| 257 ASSERT(is_uint2(scale)); | 257 ASSERT(is_uint2(scale)); |
| 258 // Use SIB with no index register only for base rsp or r12. Otherwise we | 258 // Use SIB with no index register only for base rsp or r12. Otherwise we |
| 259 // would skip the SIB byte entirely. | 259 // would skip the SIB byte entirely. |
| 260 ASSERT(!index.is(rsp) || base.is(rsp) || base.is(r12)); | 260 ASSERT(!index.is(rsp) || base.is(rsp) || base.is(r12)); |
| 261 buf_[1] = scale << 6 | (index.code() & 0x7) << 3 | (base.code() & 0x7); | 261 buf_[1] = scale << 6 | index.low_bits() << 3 | base.low_bits(); |
| 262 rex_ |= (index.code() >> 3) << 1 | base.code() >> 3; | 262 rex_ |= index.high_bit() << 1 | base.high_bit(); |
| 263 len_ = 2; | 263 len_ = 2; |
| 264 } | 264 } |
| 265 | 265 |
| 266 void Operand::set_disp8(int disp) { | 266 void Operand::set_disp8(int disp) { |
| 267 ASSERT(is_int8(disp)); | 267 ASSERT(is_int8(disp)); |
| 268 ASSERT(len_ == 1 || len_ == 2); | 268 ASSERT(len_ == 1 || len_ == 2); |
| 269 int8_t* p = reinterpret_cast<int8_t*>(&buf_[len_]); | 269 int8_t* p = reinterpret_cast<int8_t*>(&buf_[len_]); |
| 270 *p = disp; | 270 *p = disp; |
| 271 len_ += sizeof(int8_t); | 271 len_ += sizeof(int8_t); |
| 272 } | 272 } |
| 273 | 273 |
| 274 void Operand::set_disp32(int disp) { | 274 void Operand::set_disp32(int disp) { |
| 275 ASSERT(len_ == 1 || len_ == 2); | 275 ASSERT(len_ == 1 || len_ == 2); |
| 276 int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]); | 276 int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]); |
| 277 *p = disp; | 277 *p = disp; |
| 278 len_ += sizeof(int32_t); | 278 len_ += sizeof(int32_t); |
| 279 } | 279 } |
| 280 | 280 |
| 281 | 281 |
| 282 } } // namespace v8::internal | 282 } } // namespace v8::internal |
| 283 | 283 |
| 284 #endif // V8_X64_ASSEMBLER_X64_INL_H_ | 284 #endif // V8_X64_ASSEMBLER_X64_INL_H_ |
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