ST1.5 board support and some ST1.0/1.5 common changes.

include/configs/chromeos/st1q/common.h

 /*
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
  *
  * (C) Copyright 2002-2005
  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  * Gary Jennejohn <gj@denx.de>
  *
  * Configuation settings for the st1q board, based on the Qualcomm
  * QSD8x50 surf board.
@@ skipping 102 matching lines @@
 #undef  CONFIG_SILENT_CONSOLE
 #define CFG_QC_SERIAL
 #define CONFIG_CONS_INDEX               0
 #define CONFIG_BAUDRATE                 115200
 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTP_MASK               CONFIG_BOOTP_DEFAULT
 
 #define CONFIG_BOOTDELAY                0
 #define CONFIG_BOOTARGS                 "quiet root=/dev/mmcblk0p3 rootwait noresume noswap ro loglevel=1"
-#define CONFIG_BOOTCOMMAND              "if mmc init; then ext2load mmc 0:3 0x20007fc0 boot/vmlinux.uimg; bootm 0x20007fc0; fi;"
+#define CONFIG_BOOTCOMMAND              "if mmcinfo 0; then ext2load mmc 0:3 0x20007fc0 boot/vmlinux.uimg; bootm 0x20007fc0; fi;"
 
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 #define CONFIG_SYS_PROMPT       "ChromeOS> "
 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size  */
@@ skipping 22 matching lines @@
 #define CONFIG_NR_DRAM_BANKS    2
 #define PHYS_SDRAM_1            0x20000000          /* EBI1 start */
 #define PHYS_SDRAM_1_SIZE       0x0E000000          /* 256 - 32(adsp) = 224MB (0x0E000000)*/
 #define PHYS_SDRAM_2            0x30000000          /* EBI1, AFTER ADSP */
 #define PHYS_SDRAM_2_SIZE       0x30000000          /* For 1024MB on new memory map */
 
 /*
  * Use the serial console.
  */
 #define CONFIG_SERIAL_CONSOLE
-#define CONFIG_STDOUT "serial"
-#define CONFIG_STDERR "serial"
-#define CONFIG_STDIN  "serial"
+
+/* Console setup */
+#if defined(CONFIG_SERIAL_CONSOLE)
+ #define CONFIG_STDOUT "serial"
+ #define CONFIG_STDERR "serial"
+ #define CONFIG_STDIN  "serial"
+#else
+ #define CONFIG_ARM_DCC
+ #define CONFIG_ARM_DCC_MULTI
+ #define CONFIG_CPU_V7
+
+ #define CONFIG_STDOUT "dcc"
+ #define CONFIG_STDERR "dcc"
+ #define CONFIG_STDIN  "dcc"
+#endif
+
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 
 /*-----------------------------------------------------------------------
  * Shared Memory Location -
  */
 #define SMEM_START  0x00100000
 #define SMEM_SIZE   0x00100000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map -
  * U-Boot code, data, stack, etc. reside in SMI SDRAM 0x00000000-0x000FFFFF.
  * There are similar parameters in the u-boot.lds linker script which also
  * need to be updated.
  */
 #define UBOOT_SDRAM_BASE         0x00000000      /* SMI */
 #define UBOOT_SDRAM_SIZE         0x00100000
 
 /* Memory Test */
 #define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END         (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
 
 /* Environment */
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_SIZE         0x2000
 
-/* Boot parameter address */
-#define CFG_QC_BOOT_PARAM_ADDR    PHYS_SDRAM_1
+/* Boot parameter address - offset of 0x100 from base of first sdram region */
+#define CFG_QC_BOOT_PARAM_ADDR    (PHYS_SDRAM_1 + 0x100)
 
 /*-----------------------------------------------------------------------
  * The qc_serial driver uses the register names below. Set UART_BASE
  * for the desired UART.
  */
 #define UART_BASE     UART3_BASE
 
+#define CONFIG_GENERIC_MMC
+#define CONFIG_QSD_SDCC
+
+
+#ifndef CONFIG_GENERIC_MMC
+/* This section regarding legacy mmc will be removed once the new
+ * mmc framework has been verified/tested sufficiently. If there are
+ * any major issues, you could go back to the legacy mmc by undefining
+ * the generic mmc code.
+ */
 
 /*-----------------------------------------------------------------------
  * Choose the SD controller to use. SDC1, 2, 3, or 4.
  */
 #define SDC_INSTANCE  1
 #define USE_DM
 #define USE_HIGH_SPEED_MODE
 #define USE_4_BIT_BUS_MODE
 #define CONFIG_SYS_MMC_BASE             0xF0000000    // not used, but defined to prevent compile error
 #define PROC_COMM_VREG_SDC  PM_VREG_GP6_ID
+#endif
 
 /*-----------------------------------------------------------------------
  * NAND configuration
  */
 #define CONFIG_USE_ACCELERATED_PAGE_READ
 
 #define CONFIG_SYS_MAX_NAND_DEVICE  1
 #define CONFIG_SYS_NAND_BASE        0xF0000000  // not used, but defined to prevent compile error
 
 // NAND device specific register values for the NAND controller
 // These values are for the Samsung MFG=0xEC DEV=0xAA device (x8, 1.65~1.95V, 2K page)
 // NAND_DEVn_CFG0 and 1 registers. These parameters are are used for page r/w
 #define CONFIG_QC_NAND_NAND_DEVn_CFG0_VAL    0xAAD400C0
 #define CONFIG_QC_NAND_NAND_DEVn_CFG1_VAL    0x0004745C
 
 // NAND_DEVn_CFG0 and 1 registers. These parameters are are used for READ ID command
 #define CONFIG_QC_NAND_NAND_DEVn_CFG0_RD_ID_VAL    0xA2D40000;
 #define CONFIG_QC_NAND_NAND_DEVn_CFG1_RD_ID_VAL    0x0005019C;
 
 //Decide whether to use proc comm to communicate with modem
 //This will eventually go away.
 #define USE_PROC_COMM
 #define PROC_COMM_MPP_FOR_USB_VBUS PM_MPP_16
 #undef  USE_PROC_COMM_USB_PHY_RESET /* proc_comm cmd to reset phy not working
                                        rt now, but eventually it will*/
 
 #endif /* __CONFIGS_CHROMEOS_ST1Q_COMMON_H */