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| 1 /* |
| 2 * QSD8x50A_reg.h |
| 3 * QSD8x50A Register and Bit definitions |
| 4 * |
| 5 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. |
| 6 * |
| 7 * Redistribution and use in source and binary forms, with or without |
| 8 * modification, are permitted provided that the following conditions are met: |
| 9 * * Redistributions of source code must retain the above copyright |
| 10 * notice, this list of conditions and the following disclaimer. |
| 11 * * Redistributions in binary form must reproduce the above copyright |
| 12 * notice, this list of conditions and the following disclaimer in the |
| 13 * documentation and/or other materials provided with the distribution. |
| 14 * * Neither the name of Code Aurora Forum nor |
| 15 * the names of its contributors may be used to endorse or promote |
| 16 * products derived from this software without specific prior written |
| 17 * permission. |
| 18 * |
| 19 * Alternatively, provided that this notice is retained in full, this software |
| 20 * may be relicensed by the recipient under the terms of the GNU General Public |
| 21 * License version 2 ("GPL") and only version 2, in which case the provisions of |
| 22 * the GPL apply INSTEAD OF those given above. If the recipient relicenses the |
| 23 * software under the GPL, then the identification text in the MODULE_LICENSE |
| 24 * macro must be changed to reflect "GPLv2" instead of "Dual BSD/GPL". Once a |
| 25 * recipient changes the license terms to the GPL, subsequent recipients shall |
| 26 * not relicense under alternate licensing terms, including the BSD or dual |
| 27 * BSD/GPL terms. In addition, the following license statement immediately |
| 28 * below and between the words START and END shall also then apply when this |
| 29 * software is relicensed under the GPL: |
| 30 * |
| 31 * START |
| 32 * |
| 33 * This program is free software; you can redistribute it and/or modify it under |
| 34 * the terms of the GNU General Public License version 2 and only version 2 as |
| 35 * published by the Free Software Foundation. |
| 36 * |
| 37 * This program is distributed in the hope that it will be useful, but WITHOUT |
| 38 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
| 39 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more |
| 40 * details. |
| 41 * |
| 42 * You should have received a copy of the GNU General Public License along with |
| 43 * this program; if not, write to the Free Software Foundation, Inc., |
| 44 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 45 * |
| 46 * END |
| 47 * |
| 48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 49 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 52 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 58 * POSSIBILITY OF SUCH DAMAGE. |
| 59 * |
| 60 */ |
| 61 |
| 62 #ifndef __QC_8x50A_REG_H |
| 63 #define __QC_8x50A_REG_H |
| 64 |
| 65 #define NAND_FLASH_CMD (0xA0A00000) |
| 66 #define NAND_FLASH_CMD__LAST_PAGE___M 0x00000020 |
| 67 #define NAND_FLASH_CMD__PAGE_ACC___M 0x00000010 |
| 68 #define NAND_FLASH_CMD__OP_CMD__PAGE_READ 0x2 |
| 69 #define NAND_FLASH_CMD__OP_CMD__PAGE_READ_WITH_ECC 0x3 |
| 70 #define NAND_FLASH_CMD__OP_CMD__FETCH_ID 0xB |
| 71 #define NAND_FLASH_CMD__OP_CMD__RESET_NAND_FLASH_DEVICE_OR_ONENAND_REGISTER_WRI
0xD |
| 72 #define NAND_FLASH_CHIP_SELECT (0xA0A0000C) |
| 73 #define NAND_FLASH_CHIP_SELECT__DM_EN___M 0x00000004 |
| 74 #define NANDC_EXEC_CMD (0xA0A00010) |
| 75 #define NANDC_EXEC_CMD__EXEC_CMD__EXECUTE_THE_COMMAND 0x1 |
| 76 #define NAND_FLASH_STATUS (0xA0A00014) |
| 77 #define NAND_FLASH_STATUS__OP_ERR___M 0x00000010 |
| 78 #define NAND_DEVn_CFG0(n) (0xA0A00020+0x10*n) |
| 79 #define NAND_DEV0_CFG0 (0xA0A00020) |
| 80 #define NAND_DEVn_CFG1(n) (0xA0A00024+0x10*n) |
| 81 #define NAND_FLASH_READ_ID (0xA0A00040) |
| 82 #define FLASH_DEV_CMD_VLD (0xA0A000AC) |
| 83 #define FLASH_DEV_CMD_VLD__SEQ_READ_START_VLD___M 0x00000010 |
| 84 #define FLASH_DEV_CMD_VLD__ERASE_START_VLD___M 0x00000008 |
| 85 #define FLASH_DEV_CMD_VLD__WRITE_START_VLD___M 0x00000004 |
| 86 #define FLASH_DEV_CMD_VLD__READ_START_VLD___M 0x00000001 |
| 87 #define SFLASHC_BURST_CFG (0xA0A000E0) |
| 88 #define EBI2_ECC_BUF_CFG (0xA0A000F0) |
| 89 #define FLASH_BUFF0_ACC (0xA0A00100) |
| 90 #define USBH1_USB_OTG_HS_AHB_MODE (0xA0800098) |
| 91 #define USBH1_USB_OTG_HS_CAPLENGTH (0xA0800100) |
| 92 #define USBH1_USB_OTG_HS_ULPI_VIEWPORT (0xA0800170) |
| 93 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIWU___M 0x80000000 |
| 94 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIRUN___M 0x40000000 |
| 95 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIRW___M 0x20000000 |
| 96 #define USB_OTG_HS_ULPI_VIEWPORT__ULPISS___M 0x08000000 |
| 97 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIPORT___S 24 |
| 98 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIADDR___S 16 |
| 99 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIDATRD___M 0x0000FF00 |
| 100 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIDATRD___S 8 |
| 101 #define USBH1_USB_OTG_HS_PORTSC (0xA0800184) |
| 102 #define USB_OTG_HS_PORTSC__PP___M 0x00001000 |
| 103 #define USBH1_USB_OTG_HS_USBMODE (0xA08001A8) |
| 104 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIWU___M 0x80000000 |
| 105 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIRUN___M 0x40000000 |
| 106 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIRW___M 0x20000000 |
| 107 #define USB_OTG_HS_ULPI_VIEWPORT__ULPISS___M 0x08000000 |
| 108 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIPORT___S 24 |
| 109 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIADDR___S 16 |
| 110 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIDATRD___M 0x0000FF00 |
| 111 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIDATRD___S 8 |
| 112 #define USB_OTG_HS_PORTSC__PP___M 0x00001000 |
| 113 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIWU___M 0x80000000 |
| 114 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIRUN___M 0x40000000 |
| 115 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIRW___M 0x20000000 |
| 116 #define USB_OTG_HS_ULPI_VIEWPORT__ULPISS___M 0x08000000 |
| 117 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIPORT___S 24 |
| 118 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIADDR___S 16 |
| 119 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIDATRD___M 0x0000FF00 |
| 120 #define USB_OTG_HS_ULPI_VIEWPORT__ULPIDATRD___S 8 |
| 121 #define USB_OTG_HS_PORTSC__PP___M 0x00001000 |
| 122 |
| 123 /* SD Card Controller (SDC) Registers */ |
| 124 #define SDC4_BASE (0xA0600000) |
| 125 #define SDC3_BASE (0xA0500000) |
| 126 #define SDC2_BASE (0xA0400000) |
| 127 #define SDC1_BASE (0xA0300000) |
| 128 |
| 129 /* SD controller register offsets */ |
| 130 #define MCI_POWER (0x000) |
| 131 #define MCI_CLK (0x004) |
| 132 #define MCI_ARGUMENT (0x008) |
| 133 #define MCI_CMD (0x00C) |
| 134 #define MCI_RESP_CMD (0x010) |
| 135 #define MCI_RESPn(n) (0x014+4*n) |
| 136 #define MCI_RESP0 (0x014) |
| 137 #define MCI_RESP1 (0x018) |
| 138 #define MCI_RESP2 (0x01C) |
| 139 #define MCI_RESP3 (0x020) |
| 140 #define MCI_DATA_TIMER (0x024) |
| 141 #define MCI_DATA_LENGTH (0x028) |
| 142 #define MCI_DATA_CTL (0x02C) |
| 143 #define MCI_DATA_COUNT (0x030) |
| 144 #define MCI_STATUS (0x034) |
| 145 #define MCI_CLEAR (0x038) |
| 146 #define MCI_INT_MASKn(n) (0x03C+4*n) |
| 147 #define MCI_INT_MASK0 (0x03C) |
| 148 #define MCI_INT_MASK1 (0x040) |
| 149 #define MCI_FIFO_COUNT (0x044) |
| 150 #define MCI_CCS_TIMER (0x058) |
| 151 #define MCI_FIFO (0x080) |
| 152 #define MCI_TESTBUS_CONFIG (0x0CC) |
| 153 #define MCI_TEST_CTL (0x0D0) |
| 154 #define MCI_TEST_INPUT (0x0D4) |
| 155 #define MCI_TEST_OUT (0x0D8) |
| 156 #define MCI_PERPH_ID0 (0x0E0) |
| 157 #define MCI_PERPH_ID1 (0x0E4) |
| 158 #define MCI_PERPH_ID2 (0x0E8) |
| 159 #define MCI_PERPH_ID3 (0x0EC) |
| 160 #define MCI_PCELL_ID0 (0x0F0) |
| 161 #define MCI_PCELL_ID1 (0x0F4) |
| 162 #define MCI_PCELL_ID2 (0x0F8) |
| 163 #define MCI_PCELL_ID3 (0x0FC) |
| 164 |
| 165 /* SDCC Register masks, shifts */ |
| 166 #define MCI_POWER__CONTROL__POWERON 0x3 |
| 167 #define MCI_CLK__SELECT_IN___M 0x0000C000 |
| 168 #define MCI_CLK__SELECT_IN___S 14 |
| 169 #define MCI_CLK__SELECT_IN__ON_THE_FALLING_EDGE_OF_MCICLOCK 0x0 |
| 170 #define MCI_CLK__SELECT_IN__USING_FEEDBACK_CLOCK 0x2 |
| 171 #define MCI_CLK__FLOW_ENA___M 0x00001000 |
| 172 #define MCI_CLK__WIDEBUS___M 0x00000C00 |
| 173 #define MCI_CLK__WIDEBUS___S 10 |
| 174 #define MCI_CLK__WIDEBUS__4_BIT_MODE 0x2 |
| 175 #define MCI_CLK__PWRSAVE___M 0x00000200 |
| 176 #define MCI_CLK__ENABLE___M 0x00000100 |
| 177 #define MCI_CMD__DAT_CMD___M 0x00001000 |
| 178 #define MCI_CMD__PROG_ENA___M 0x00000800 |
| 179 #define MCI_CMD__ENABLE___M 0x00000400 |
| 180 #define MCI_CMD__INTERRUPT___M 0x00000100 |
| 181 #define MCI_CMD__LONGRSP___M 0x00000080 |
| 182 #define MCI_CMD__RESPONSE___M 0x00000040 |
| 183 #define MCI_CMD__CMD_INDEX___M 0x0000003F |
| 184 #define MCI_DATA_CTL__BLOCKSIZE___S 4 |
| 185 #define MCI_DATA_CTL__DM_ENABLE___M 0x00000008 |
| 186 #define MCI_DATA_CTL__DIRECTION___M 0x00000002 |
| 187 #define MCI_DATA_CTL__ENABLE___M 0x00000001 |
| 188 #define MCI_STATUS__PROG_DONE___M 0x00800000 |
| 189 #define MCI_STATUS__RXDATA_AVLBL___M 0x00200000 |
| 190 #define MCI_STATUS__TXFIFO_FULL___M 0x00010000 |
| 191 #define MCI_STATUS__RXACTIVE___M 0x00002000 |
| 192 #define MCI_STATUS__DATA_BLK_END___M 0x00000400 |
| 193 #define MCI_STATUS__DATA_BLK_END___S 10 |
| 194 #define MCI_STATUS__START_BIT_ERR___M 0x00000200 |
| 195 #define MCI_STATUS__START_BIT_ERR___S 9 |
| 196 #define MCI_STATUS__DATAEND___M 0x00000100 |
| 197 #define MCI_STATUS__CMD_SENT___M 0x00000080 |
| 198 #define MCI_STATUS__CMD_RESPONSE_END___M 0x00000040 |
| 199 #define MCI_STATUS__CMD_RESPONSE_END___S 6 |
| 200 #define MCI_STATUS__RX_OVERRUN___M 0x00000020 |
| 201 #define MCI_STATUS__RX_OVERRUN___S 5 |
| 202 #define MCI_STATUS__TX_UNDERRUN___M 0x00000010 |
| 203 #define MCI_STATUS__TX_UNDERRUN___S 4 |
| 204 #define MCI_STATUS__DATA_TIMEOUT___M 0x00000008 |
| 205 #define MCI_STATUS__DATA_TIMEOUT___S 3 |
| 206 #define MCI_STATUS__CMD_TIMEOUT___M 0x00000004 |
| 207 #define MCI_STATUS__CMD_TIMEOUT___S 2 |
| 208 #define MCI_STATUS__DATA_CRC_FAIL___M 0x00000002 |
| 209 #define MCI_STATUS__DATA_CRC_FAIL___S 1 |
| 210 #define MCI_STATUS__CMD_CRC_FAIL___M 0x00000001 |
| 211 #define MCI_STATUS__CMD_CRC_FAIL___S 0 |
| 212 #define MCI_CLEAR__PROG_DONE_CLR___M 0x00800000 |
| 213 #define MCI_CLEAR__DATA_BLK_END_CLR___M 0x00000400 |
| 214 #define MCI_CLEAR__START_BIT_ERR_CLR___M 0x00000200 |
| 215 #define MCI_CLEAR__DATA_END_CLR___M 0x00000100 |
| 216 #define MCI_CLEAR__CMD_SENT_CLR___M 0x00000080 |
| 217 #define MCI_CLEAR__CMD_RESP_END_CLT___M 0x00000040 |
| 218 #define MCI_CLEAR__RX_OVERRUN_CLR___M 0x00000020 |
| 219 #define MCI_CLEAR__TX_UNDERRUN_CLR___M 0x00000010 |
| 220 #define MCI_CLEAR__DATA_TIMEOUT_CLR___M 0x00000008 |
| 221 #define MCI_CLEAR__CMD_TIMOUT_CLR___M 0x00000004 |
| 222 #define MCI_CLEAR__DATA_CRC_FAIL_CLR___M 0x00000002 |
| 223 #define MCI_CLEAR__CMD_CRC_FAIL_CLR___M 0x00000001 |
| 224 |
| 225 |
| 226 #define EBI2CS7_BASE (0x70000000) |
| 227 #define EBI2CS6_BASE (0x60000000) |
| 228 #define EBI2CS5_BASE (0x94000000) |
| 229 #define EBI2CS4_BASE (0x90000000) |
| 230 #define EBI2CS3_BASE (0x8C000000) |
| 231 #define EBI2CS2_BASE (0x88000000) |
| 232 #define EBI2CS1_BASE (0x84000000) |
| 233 #define EBI2CS0_BASE (0x80000000) |
| 234 #define MDP_LCDC_EN (0xAA2E0000) |
| 235 #define MDP_LCDC_HSYNC_CTL (0xAA2E0004) |
| 236 #define MDP_LCDC_VSYNC_PERIOD (0xAA2E0008) |
| 237 #define MDP_LCDC_VSYNC_PULSE_WIDTH (0xAA2E000C) |
| 238 #define MDP_LCDC_DISPLAY_HCTL (0xAA2E0010) |
| 239 #define MDP_LCDC_DISPLAY_V_START (0xAA2E0014) |
| 240 #define MDP_LCDC_DISPLAY_V_END (0xAA2E0018) |
| 241 #define MDP_LCDC_ACTIVE_HCTL (0xAA2E001C) |
| 242 #define MDP_LCDC_ACTIVE_V_START (0xAA2E0020) |
| 243 #define MDP_LCDC_ACTIVE_V_END (0xAA2E0024) |
| 244 #define MDP_LCDC_BORDER_CLR (0xAA2E0028) |
| 245 #define MDP_LCDC_UNDERFLOW_CTL (0xAA2E002C) |
| 246 #define MDP_LCDC_HSYNC_SKEW (0xAA2E0030) |
| 247 #define MDP_LCDC_CTL_POLARITY (0xAA2E0038) |
| 248 #define MDP_DMA_P_CONFIG (0xAA290000) |
| 249 #define MDP_DMA_P_SIZE (0xAA290004) |
| 250 #define MDP_DMA_P_IBUF_ADDR (0xAA290008) |
| 251 #define MDP_DMA_P_IBUF_Y_STRIDE (0xAA29000C) |
| 252 #define MDP_DMA_P_OUT_XY (0xAA290010) |
| 253 #define UART3_BASE (0xA9C00000) |
| 254 #define UART_SR__TXRDY___M 0x00000004 |
| 255 #define UART_SR__RXRDY___M 0x00000001 |
| 256 #define UART2_BASE (0xA9B00000) |
| 257 #define UART_SR__TXRDY___M 0x00000004 |
| 258 #define UART_SR__RXRDY___M 0x00000001 |
| 259 #define UART1_BASE (0xA9A00000) |
| 260 #define UART_SR__TXRDY___M 0x00000004 |
| 261 #define UART_SR__RXRDY___M 0x00000001 |
| 262 #define HI0_CHn_CMD_PTR_SD3(n) (0xA9700C00+4*n) |
| 263 #define HI0_CHn_RSLT_SD3(n) (0xA9700C40+4*n) |
| 264 #define HI0_CHn_RSLT_SD3__V___M 0x80000000 |
| 265 #define HI0_CHn_RSLT_SD3__ERR___M 0x00000008 |
| 266 #define HI0_CHn_RSLT_SD3__TPD___M 0x00000002 |
| 267 #define HI0_CH8_RSLT_CONF_SD3 (0xA9700F20) |
| 268 #define HI0_CHn_STATUS_SD3(n) (0xA9700E00+4*n) |
| 269 #define HI0_CHn_STATUS_SD3__RSLT_VLD___M 0x00000002 |
| 270 #define GPIO_OUT_1 (0xA8F00400) |
| 271 #define GPIO_OUT_0 (0xA8E00000) |
| 272 #define GPIO1_PAGE (0xA8E00040) |
| 273 #define GPIO1_CFG (0xA8E00044) |
| 274 #define GLBL_CLK_ENA (0xA8600000) |
| 275 #define GLBL_CLK_ENA__SDC4_H_CLK_ENA___M 0x10000000 |
| 276 #define GLBL_CLK_ENA__SDC3_H_CLK_ENA___M 0x08000000 |
| 277 #define GLBL_CLK_ENA__SDC2_H_CLK_ENA___M 0x00000100 |
| 278 #define GLBL_CLK_ENA__SDC1_H_CLK_ENA___M 0x00000080 |
| 279 #define PRPH_WEB_NS_REG (0xA8600080) |
| 280 #define SDC1_MD_REG (0xA86000A0) |
| 281 #define SDC1_NS_REG (0xA86000A4) |
| 282 #define SDC2_MD_REG (0xA86000A8) |
| 283 #define SDC2_NS_REG (0xA86000AC) |
| 284 #define UART_NS_REG (0xA86000C0) |
| 285 #define UART_NS_REG__UART3_SRC_SEL___M 0x00007000 |
| 286 #define UART_NS_REG__UART3_SRC_SEL___S 12 |
| 287 #define UART_NS_REG__UART2_SRC_SEL___M 0x000001C0 |
| 288 #define UART_NS_REG__UART2_SRC_SEL___S 6 |
| 289 #define UART_NS_REG__UART1_SRC_SEL___M 0x00000007 |
| 290 #define UART_NS_REG__UART1_SRC_SEL___S 0 |
| 291 #define MSS_RESET (0xA8600204) |
| 292 #define APPS_RESET (0xA8600214) |
| 293 #define APPS_RESET__USB_PHY___M 0x00040000 |
| 294 #define APPS_RESET__USBH___M 0x00008000 |
| 295 #define ROW_RESET (0xA8600218) |
| 296 #define ROW_RESET__SDC4___M 0x10000000 |
| 297 #define ROW_RESET__SDC3___M 0x08000000 |
| 298 #define ROW_RESET__SDC1___M 0x00000200 |
| 299 #define ROW_RESET__SDC2___M 0x00000100 |
| 300 #define SDC3_MD_REG (0xA86003D4) |
| 301 #define SDC3_NS_REG (0xA86003D8) |
| 302 #define SDC4_MD_REG (0xA86003DC) |
| 303 #define SDC4_NS_REG (0xA86003E0) |
| 304 #define USBH_NS_REG (0xA86003E8) |
| 305 #define LCD_MD_REG (0xA86003EC) |
| 306 #define LCD_NS_REG (0xA86003F0) |
| 307 #define PLL_DEBUG (0xA8800000) |
| 308 #define PLL_CTL (0xA8800004) |
| 309 #define PLL_CTL__BYPASSNL___M 0x00400000 |
| 310 #define PLL_CTL__RESET_N___M 0x00200000 |
| 311 #define PLL_CTL__PLL_MODE__POWER_DOWN 0x0 |
| 312 #define PLL_CTL__PLL_MODE__STAND_BY 0x2 |
| 313 #define PLL_CTL__PLL_MODE__FULL_CALIBRATION 0x4 |
| 314 #define PLL_CTL__PLL_MODE__NORMAL_OPERATION 0x7 |
| 315 #define PLL_FSM_CTL_EXT (0xA8800024) |
| 316 #define PLL_FSM_CTL_EXT__STATIC_BITS 0x00140000 |
| 317 #define PLL_FSM_CTL_EXT__TARG_L_VAL___S 3 |
| 318 #define PLL_FSM_CTL_EXT__FRESWI_MODE__SHOT 0x4 |
| 319 #define PLL_FSM_CTL_EXT__FRESWI_MODE__HOP 0x5 |
| 320 #define PLL_STATUS (0xA8800010) |
| 321 #define PLL_STATUS__CAL_ALL_DONE_N___M 0x00000002 |
| 322 #define PLL_STATUS__SWITCH_IN_PROGRESS_N___M 0x00000003 |
| 323 #define PLL_CAL (0xA8800008) |
| 324 #define AGPT_MATCH_VAL (0xAC100000) |
| 325 #define AGPT_COUNT_VAL (0xAC100004) |
| 326 #define AGPT_ENABLE (0xAC100008) |
| 327 #define AGPT_ENABLE__CLR_ON_MATCH_EN___M 0x00000002 |
| 328 #define AGPT_ENABLE__EN___M 0x00000001 |
| 329 #define AGPT_CLEAR (0xAC10000C) |
| 330 #define AST_ENABLE (0xAC10002C) |
| 331 #define SPSS_CLK_SEL (0xAC100104) |
| 332 #define TCSR_SPARE2 (0xA8700060) |
| 333 #define A2M_INT0 (0xAC100400) |
| 334 #define A2M_INT1 (0xAC100404) |
| 335 #define A2M_INT2 (0xAC100408) |
| 336 #define A2M_INT3 (0xAC10040C) |
| 337 #define A2M_INT4 (0xAC100410) |
| 338 #define A2M_INT5 (0xAC100414) |
| 339 #define A2M_INT6 (0xAC100418) |
| 340 |
| 341 #endif /* __QC_8x50A_REG_H */ |
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