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Side by Side Diff: drivers/mmc/qsd_sdcc.c

Issue 1329001: ST1.5 board support and some ST1.0/1.5 common changes. (Closed)
Patch Set: Created 10 years, 9 months ago
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1 /* 1 /*
2 Copyright (c) 2010, Code Aurora Forum. All rights reserved. 2 Copyright (c) 2010, Code Aurora Forum. All rights reserved.
3 3
4 This program is free software; you can redistribute it and/or modify 4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License version 2 and 5 it under the terms of the GNU General Public License version 2 and
6 only version 2 as published by the Free Software Foundation. 6 only version 2 as published by the Free Software Foundation.
7 7
8 This program is distributed in the hope that it will be useful, 8 This program is distributed in the hope that it will be useful,
9 but WITHOUT ANY WARRANTY; without even the implied warranty of 9 but WITHOUT ANY WARRANTY; without even the implied warranty of
10 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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148 } 148 }
149 149
150 #ifdef CONFIG_DCACHE 150 #ifdef CONFIG_DCACHE
151 /* Invalidate cache so buffer ADM updated can be seen. */ 151 /* Invalidate cache so buffer ADM updated can be seen. */
152 invalidate_dcache_range((uint32_t)data->dest, 152 invalidate_dcache_range((uint32_t)data->dest,
153 (uint32_t)data->dest + (data->blocks * data->blo cksize)); 153 (uint32_t)data->dest + (data->blocks * data->blo cksize));
154 #endif 154 #endif
155 } 155 }
156 else 156 else
157 { 157 {
158 int read_len = ( (data->blocks) * data->blocksize);
159
158 while( (status = IO_READ32(base + MCI_STATUS)) & MCI_STATUS_READ_DATA_MA SK) 160 while( (status = IO_READ32(base + MCI_STATUS)) & MCI_STATUS_READ_DATA_MA SK)
159 { 161 {
160 if(status & MCI_STATUS__RXDATA_AVLBL___M) 162 if(byte_count < read_len)
161 { 163 {
162 *dest_ptr = IO_READ32(base + MCI_FIFO); 164 if(status & MCI_STATUS__RXDATA_AVLBL___M)
163 dest_ptr++; 165 {
164 byte_count += 4; 166 *dest_ptr = IO_READ32(base + MCI_FIFO);
167 dest_ptr++;
168 byte_count += 4;
169 }
165 } 170 }
166 } 171 }
167 } 172 }
168 return sdcc_read_data_cleanup(mmc); 173 return sdcc_read_data_cleanup(mmc);
169 } 174 }
170 175
171 /* Set SD MCLK speed */ 176 /* Set SD MCLK speed */
172 static int sdcc_mclk_set(int instance, enum SD_MCLK_speed speed) 177 static int sdcc_mclk_set(int instance, enum SD_MCLK_speed speed)
173 { 178 {
174 #ifndef USE_PROC_COMM 179 #ifndef USE_PROC_COMM
175 #error "use proc_comm" 180 #error "use proc_comm"
176 #else 181 #else
177 /* SDCn_NS_REG clk enable bits are turned on automatically as part of */
178 /* setting clk speed. No need to enable sdcard clk explicitely */
179 proc_comm_set_sdcard_clk(instance, speed); 182 proc_comm_set_sdcard_clk(instance, speed);
183 proc_comm_enable_sdcard_clk(instance);
180 #endif /*USE_PROC_COMM*/ 184 #endif /*USE_PROC_COMM*/
181 185
182 return 0; 186 return 0;
183 } 187 }
184 188
185 /* Set bus width and bus clock speed */ 189 /* Set bus width and bus clock speed */
186 void sdcc_set_ios(struct mmc *mmc) 190 void sdcc_set_ios(struct mmc *mmc)
187 { 191 {
188 uint32_t clk_reg; 192 uint32_t clk_reg;
189 uint32_t base = ((sdcc_params_t*)(mmc->priv))->base; 193 uint32_t base = ((sdcc_params_t*)(mmc->priv))->base;
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481 { 485 {
482 /* error */ 486 /* error */
483 return -1; 487 return -1;
484 } 488 }
485 489
486 /* Enable clock */ 490 /* Enable clock */
487 proc_comm_enable_sdcard_pclk(sd->instance); 491 proc_comm_enable_sdcard_pclk(sd->instance);
488 492
489 /* Set the interface clock */ 493 /* Set the interface clock */
490 proc_comm_set_sdcard_clk(sd->instance, MCLK_400KHz); 494 proc_comm_set_sdcard_clk(sd->instance, MCLK_400KHz);
495 proc_comm_enable_sdcard_clk(sd->instance);
496
491 497
492 /* Initialize controller */ 498 /* Initialize controller */
493 sdcc_controller_init(sd); 499 sdcc_controller_init(sd);
494 500
495 return 0; 501 return 0;
496 } 502 }
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