OLD | NEW |
1 /* | 1 /* |
2 * Copyright (c) 2009, Code Aurora Forum. All rights reserved. | 2 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. |
3 * | 3 * |
4 * (C) Copyright 2002 | 4 * (C) Copyright 2002 |
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | 5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
6 * Marius Groeger <mgroeger@sysgo.de> | 6 * Marius Groeger <mgroeger@sysgo.de> |
7 * | 7 * |
8 * (C) Copyright 2002 | 8 * (C) Copyright 2002 |
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> | 9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
10 * | 10 * |
11 * (C) Copyright 2003 | 11 * (C) Copyright 2003 |
12 * Texas Instruments, <www.ti.com> | 12 * Texas Instruments, <www.ti.com> |
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
54 bd->bi_dram[bank_num].start = start_addr; | 54 bd->bi_dram[bank_num].start = start_addr; |
55 bd->bi_dram[bank_num].size = size; | 55 bd->bi_dram[bank_num].size = size; |
56 | 56 |
57 /* | 57 /* |
58 * Map new region in MMU. | 58 * Map new region in MMU. |
59 */ | 59 */ |
60 mmu_map_region(bd->bi_dram[bank_num].start, | 60 mmu_map_region(bd->bi_dram[bank_num].start, |
61 bd->bi_dram[bank_num].size, | 61 bd->bi_dram[bank_num].size, |
62 MEM_TYPE_KERNEL); | 62 MEM_TYPE_KERNEL); |
63 | 63 |
64 /* | |
65 * ATAGs are always at the base of the first sd ram region. | |
66 * If that is changing, update the resulting ATAG address | |
67 */ | |
68 if (0 == bank_num) { | |
69 bd->bi_boot_params = start_addr; | |
70 } | |
71 | |
72 return 0; | 64 return 0; |
73 } | 65 } |
74 | 66 |
75 int dram_init (void) | 67 int dram_init (void) |
76 { | 68 { |
77 dram_reinit(PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE, 0); | 69 dram_reinit(PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE, 0); |
78 #if CONFIG_NR_DRAM_BANKS >= 2 | 70 #if CONFIG_NR_DRAM_BANKS >= 2 |
79 dram_reinit(PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE, 1); | 71 dram_reinit(PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE, 1); |
80 #endif | 72 #endif |
| 73 #if CONFIG_NR_DRAM_BANKS >= 3 |
| 74 dram_reinit(PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE, 2); |
| 75 #endif |
81 return 0; | 76 return 0; |
82 } | 77 } |
83 | 78 |
OLD | NEW |