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1 // Copyright 2009 the V8 project authors. All rights reserved. | 1 // Copyright 2009 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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244 UNIMPLEMENTED(); // IA32 code below. | 244 UNIMPLEMENTED(); // IA32 code below. |
245 ASSERT(IsCallInstruction()); | 245 ASSERT(IsCallInstruction()); |
246 return reinterpret_cast<Object**>(pc_ + 1); | 246 return reinterpret_cast<Object**>(pc_ + 1); |
247 } | 247 } |
248 | 248 |
249 // ----------------------------------------------------------------------------- | 249 // ----------------------------------------------------------------------------- |
250 // Implementation of Operand | 250 // Implementation of Operand |
251 | 251 |
252 void Operand::set_modrm(int mod, Register rm) { | 252 void Operand::set_modrm(int mod, Register rm) { |
253 ASSERT((mod & -4) == 0); | 253 ASSERT((mod & -4) == 0); |
254 buf_[0] = mod << 6 | (rm.code() & 0x7); | 254 buf_[0] = (mod << 6) | (rm.code() & 0x7); |
255 // Set REX.B to the high bit of rm.code(). | 255 // Set REX.B to the high bit of rm.code(). |
256 rex_ |= (rm.code() >> 3); | 256 rex_ |= (rm.code() >> 3); |
257 } | 257 } |
258 | 258 |
259 | 259 |
260 void Operand::set_sib(ScaleFactor scale, Register index, Register base) { | 260 void Operand::set_sib(ScaleFactor scale, Register index, Register base) { |
261 ASSERT(len_ == 1); | 261 ASSERT(len_ == 1); |
262 ASSERT(is_uint2(scale)); | 262 ASSERT(is_uint2(scale)); |
263 // Use SIB with no index register only for base rsp or r12. | 263 // Use SIB with no index register only for base rsp or r12. |
264 ASSERT(!index.is(rsp) || base.is(rsp) || base.is(r12)); | 264 ASSERT(!index.is(rsp) || base.is(rsp) || base.is(r12)); |
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279 ASSERT(len_ == 1 || len_ == 2); | 279 ASSERT(len_ == 1 || len_ == 2); |
280 int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]); | 280 int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]); |
281 *p = disp; | 281 *p = disp; |
282 len_ += sizeof(int32_t); | 282 len_ += sizeof(int32_t); |
283 } | 283 } |
284 | 284 |
285 | 285 |
286 } } // namespace v8::internal | 286 } } // namespace v8::internal |
287 | 287 |
288 #endif // V8_X64_ASSEMBLER_X64_INL_H_ | 288 #endif // V8_X64_ASSEMBLER_X64_INL_H_ |
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