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Side by Side Diff: src/arm/constants-arm.h

Issue 119036: * Modify simulator and ARM code generator to avoid swi... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 11 years, 6 months ago
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1 // Copyright 2008 the V8 project authors. All rights reserved. 1 // Copyright 2008 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 27
28 #ifndef V8_ARM_CONSTANTS_ARM_H_ 28 #ifndef V8_ARM_CONSTANTS_ARM_H_
29 #define V8_ARM_CONSTANTS_ARM_H_ 29 #define V8_ARM_CONSTANTS_ARM_H_
30 30
31 // The simulator emulates the EABI so we define the __ARM_EABI__ macro if we
32 // are not running on real ARM hardware. One reason for this is that the
33 // old ABI uses fp registers in the calling convention and the simulator does
34 // not simulate fp registers or coroutine instructions.
35 #ifndef __arm__
36 # ifdef __ARM_EABI__
37 # undef __ARM_EABI__
38 # endif
39 # define __ARM_EABI__ 1
iposva 2009/06/08 21:48:41 It makes me a bit uncomfortable to be defining "co
Erik Corry 2009/06/09 09:27:00 Fixed with the introduction of USE_ARM_EABI macro
40 #endif
41
31 namespace assembler { 42 namespace assembler {
32 namespace arm { 43 namespace arm {
33 44
34 // Defines constants and accessor classes to assemble, disassemble and 45 // Defines constants and accessor classes to assemble, disassemble and
35 // simulate ARM instructions. 46 // simulate ARM instructions.
36 // 47 //
37 // Section references in the code refer to the "ARM Architecture Reference 48 // Section references in the code refer to the "ARM Architecture Reference
38 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) 49 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
39 // 50 //
40 // Constants for specific fields are defined in their respective named enums. 51 // Constants for specific fields are defined in their respective named enums.
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97 ASR = 2, // Arithmetic shift right 108 ASR = 2, // Arithmetic shift right
98 ROR = 3, // Rotate right 109 ROR = 3, // Rotate right
99 max_shift = 4 110 max_shift = 4
100 }; 111 };
101 112
102 113
103 // Special Software Interrupt codes when used in the presence of the ARM 114 // Special Software Interrupt codes when used in the presence of the ARM
104 // simulator. 115 // simulator.
105 enum SoftwareInterruptCodes { 116 enum SoftwareInterruptCodes {
106 // transition to C code 117 // transition to C code
107 call_rt_r5 = 0x10, 118 call_rt_redirected = 0x10,
108 call_rt_r2 = 0x11,
109 // break point 119 // break point
110 break_point = 0x20, 120 break_point = 0x20
111 // FP operations. These simulate calling into C for a moment to do fp ops.
112 // They should trash all caller-save registers.
113 simulator_fp_add = 0x21,
114 simulator_fp_sub = 0x22,
115 simulator_fp_mul = 0x23
116 }; 121 };
117 122
118 123
119 typedef int32_t instr_t; 124 typedef int32_t instr_t;
120 125
121 126
122 // The class Instr enables access to individual fields defined in the ARM 127 // The class Instr enables access to individual fields defined in the ARM
123 // architecture instruction set encoding as described in figure A3-1. 128 // architecture instruction set encoding as described in figure A3-1.
124 // 129 //
125 // Example: Test whether the instruction at ptr does set the condition code 130 // Example: Test whether the instruction at ptr does set the condition code
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232 237
233 private: 238 private:
234 // We need to prevent the creation of instances of class Instr. 239 // We need to prevent the creation of instances of class Instr.
235 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 240 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
236 }; 241 };
237 242
238 243
239 } } // namespace assembler::arm 244 } } // namespace assembler::arm
240 245
241 #endif // V8_ARM_CONSTANTS_ARM_H_ 246 #endif // V8_ARM_CONSTANTS_ARM_H_
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